LabVIEW FPGA Error Code Family

From LabVIEW Wiki
Jump to: navigation, search

Below are all of the Error Codes that belong to the LabVIEW FPGA Error Code Family (see Error List for list of Families).

Code Description
-61515 LabVIEW FPGA: Local variables are not allowed in the top-level VI in IP export.
-61514 LabVIEW FPGA: This function or VI is not allowed in IP export.
-61513 LabVIEW FPGA: This node is not allowed in IP export.
-61512 LabVIEW FPGA: The destination directory path cannot contain parentheses.
-61511 LabVIEW FPGA: Unsupported file type.
-61510 LabVIEW FPGA: Cannot access distributed RAM from different clock domains.
-61509 LabVIEW FPGA: Unsupported number of elements per read or write on the current target.
-61508 LabVIEW FPGA: Node not supported in single-cycle Timed Loops.
-61507 LabVIEW FPGA: Peer-to-peer FIFOs are unsupported on the current target.
-61506 LabVIEW FPGA: The FPGA VI configured for running in simulation mode contains controls or indicators with duplicate names. The Read/Write function cannot read from or write to controls or indicators with duplicate names. Rename the controls or indicators.
-61505 LabVIEW FPGA: Unsupported .xci file.
-61504 LabVIEW FPGA: Unsupported FIFO method.
-61503 LabVIEW FPGA: Missing required Xilinx compilation tools.
-61502 LabVIEW FPGA: File format mismatch.
-61501 LabVIEW FPGA: Internal software error(s).
-61500 LabVIEW FPGA: An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:

LabVIEW could not read a CLIP XML file.

-61499 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
-61498 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

Required tag was not found in the resource file.

-61497 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

An unsupported register offset was requested.

-61496 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

An unexpected case was reached.

-61495 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

A path tag specified a value that is not a path.

-61494 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

An IP Generator VI did not match the required interface.

-61493 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

The specified IP Generator VI could not be found.

-61492 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

Error accessing FPGA provider.

-61491 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

An IP Generator is missing the required VI Path Tag.

-61490 LabVIEW FPGA: An internal error has occurred.
-61489 LabVIEW FPGA: Internal software error(s).
-61488 LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information:

A required XML tag was not found.

-61487 LabVIEW FPGA: This channel control or indicator is on the top-level VI.
-61475 LabVIEW FPGA: The XML tag "DramAddressBitAlignment" is missing from the target resource XML file. For more details consult LabVIEW_FPGA_PlugInManual.doc.
-61474 LabVIEW FPGA: "FFT size" must be greater than or equal to the number of samples per input.
-61473 LabVIEW FPGA: The "imaginary data" input array size is different from that of the "real data" input. The array sizes of these inputs must be the same.
-61472 LabVIEW FPGA: The input array size must be 2, 4, 8, or 16.
-61471 LabVIEW FPGA: You must reload the IO Module declaration file.
-61470 LabVIEW FPGA: You must reload the DRAM declaration file.
-61469 LabVIEW FPGA: Invalid size for Stream or Lossy Stream channel writer.
-61468 LabVIEW FPGA: A channel terminal of a non-reentrant subVI is connected to multiple channels.
-61467 LabVIEW FPGA: Stream or Lossy Stream writer endpoints not wired correctly.
-61466 LabVIEW FPGA: LabVIEW encountered an error when trying to run the Vivado Design Suite scripts.
-61465 LabVIEW FPGA: LabVIEW failed to delete a file.
-61464 LabVIEW FPGA: LabVIEW failed to delete a file.
-61463 LabVIEW FPGA: LabVIEW failed to export project for the Vivado Design Suite.
-61462 LabVIEW FPGA: The design was unable to meet timing requirements due to a pulse width violation.
-61461 LabVIEW FPGA: This version of LabVIEW does not support the requested FPGA compilation tools.
-61460 LabVIEW FPGA: Control and indicator names with newline characters are only supported when the VI execution mode is set to Simulation (Simulated I/O) and the FPGA VI reference is configured for Dynamic mode.
-61459 LabVIEW FPGA: The selected target requires 64-bit Xilinx tools, but the system uses a 32-bit OS.
-61458 LabVIEW FPGA: Target does not support terminals configured for variable and bounded size arrays.
-61457 LabVIEW FPGA: The compilation status file is missing or corrupt.
-61456 LabVIEW FPGA: The FPGA design did not meet timing requirements and the source of the timing failure could not be located automatically.
-61455 LabVIEW FPGA: Some of the compilation steps were not executed.
-61454 LabVIEW FPGA: Some signals were not properly constrained in the design.
-61453 LabVIEW FPGA: The constraints file was not used in the compilation.
-61452 LabVIEW FPGA: The compilation failed due to resource overmapping.
-61451 LabVIEW FPGA: The compilation failed due to timing violations.
-61450 LabVIEW FPGA: The compilation failed due to a Xilinx error.
-61449 LabVIEW FPGA: The FPGA VI has finished executing.
-61448 LabVIEW FPGA: The simulation is not running.
-61447 LabVIEW FPGA: LabVIEW cannot locate the VI.
-61446 LabVIEW FPGA: The execution mode is invalid for the Desktop Execution Node.
-61445 LabVIEW FPGA: The handshake is outside a single-cycle Timed Loop.
-61444 LabVIEW FPGA: The Desktop Execution Node is misconfigured.
-61443 LabVIEW FPGA: The simulation has exceeded the maximum simulated time.
-61442 LabVIEW FPGA: The FPGA Desktop Execution Node cannot run the configured VI.
-61441 LabVIEW FPGA: Another FPGA VI for this target is already executing on the development computer. Stop the other VI before running this VI.
-61417 LabVIEW FPGA: The method does not support FIFOs with the "UltraRAM" implementation.
-61416 LabVIEW FPGA: The current target does not support FIFOs with the UltraRAM implementation.
-61415 LabVIEW FPGA: The method does not support FIFOs with the "Built-In" control logic.
-61414 LabVIEW FPGA: Control or indicator data type is not supported.
-61413 LabVIEW FPGA: FIFO with handshaking interface is outside a single-cycle Timed Loop.
-61412 LabVIEW FPGA: Missing feedback node after Ready For Input terminal.
-61411 LabVIEW FPGA: FIFO invokes methods with incompatible interfaces.
-61410 LabVIEW FPGA: Target does not support the handshaking interface on this FIFO.
-61408 LabVIEW FPGA: Feedback Node initialization unsupported.
-61406 LabVIEW FPGA: The logic in a socketed CLIP is preventing the FPGA VI from running.
-61405 LabVIEW FPGA: The operation failed because you do not have a physical target specified for this FPGA target.

Right-click the FPGA target in the Project Explorer window, select Properties, and enter an FPGA target resource name in the Resource text box.

-61404 LabVIEW FPGA: LabVIEW encountered a target-specific error or warning.
-61403 LabVIEW FPGA: LabVIEW is unable to interact with the current target because a required file is missing or inaccessible. Check that the FPGA target-specific driver software is installed correctly.
-61402 LabVIEW FPGA: LabVIEW lost communication with the device.

The resource for the target was disconnected or removed.

If the target is located remotely, the remote system might be turned off or there might be a network problem.

-61400 LabVIEW FPGA: Operation failed because the type of the hardware specified in the project and/or in the VI does not match the type of the hardware that was physically accessed.
-61399 LabVIEW FPGA: Execution of the FPGA VI on the development computer is not supported for the given item/node in the custom VI used for FPGA I/O.
-61398 LabVIEW FPGA: FPGA VI simulation failed because either the path for the specified custom VI for FPGA I/O simulation is missing or incorrect, or the specified custom VI for FPGA I/O simulation uses an incorrect connector pane. Check the custom VI path on the Simulation page of the target settings or check that the VI matches the required interface.
-61397 LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O does not conform to the calling requirements of the FPGA VI.
-61396 LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O called a VI or a function that returned an error.
-61395 LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O is not executable.
-61394 LabVIEW FPGA: This VI is supported only when the Execution Stage is Running.
-61355 LabVIEW FPGA: An internal software error has occurred. DFIR refnum not found.
-61354 LabVIEW FPGA: Internal software error(s): Connected node is not constant.
-61353 LabVIEW FPGA: Internal software error(s): Output terminal not supported.
-61352 LabVIEW FPGA: Internal software error(s): Terminal is not connectable.
-61351 LabVIEW FPGA: Internal software error(s): Terminal is unconnected.
-61350 LabVIEW FPGA: Internal software error(s): Terminal Index Out of Bounds.
-61347 LabVIEW FPGA: The user has reached the maximum number of simultaneous compiles for this compile cloud account.
-61346 LabVIEW FPGA: The FPGA Compile Farm Server does not support the current version of the FPGA Module. Use a compatible version of the FPGA Compile Farm Server or switch to another server. Refer to the FPGA Module readme for information about FPGA Module versions supported by this version of FPGA Compile Farm Server.
-61345 LabVIEW FPGA: Unresolved LabVIEW class.
-61344 LabVIEW FPGA: The array contains arrays of varying sizes.
-61343 LabVIEW FPGA: Unresolved LabVIEW class.
-61342 LabVIEW FPGA: The compile farm server returned an unexpected software error.
-61341 LabVIEW FPGA: The array contains arrays of varying sizes.
-61340 LabVIEW FPGA: The compilation failed because the system ran out of memory.
-61339 LabVIEW FPGA: The top-level VI contains a variable-sized array control or indicator.
-61338 LabVIEW FPGA: Array does not resolve to a fixed size.
-61337 LabVIEW FPGA: Array does not resolve to a fixed size.
-61336 LabVIEW FPGA: The While Loop contains an auto-indexed output tunnel.
-61335 LabVIEW FPGA: Array does not resolve to a fixed size.
-61334 LabVIEW FPGA: Array does not resolve to a fixed size.
-61333 LabVIEW FPGA: Array does not resolve to a fixed size.
-61332 LabVIEW FPGA: An unexpected error occurred with the compilation tools. Trying to compile the FPGA VI again might resolve the issue.
-61331 LabVIEW FPGA: The UnitOfWork file sent to the Compile Worker was malformed.
-61330 LabVIEW FPGA: An internal software error in the compile worker has occurred.
-61329 LabVIEW FPGA: The LabVIEW FPGA Module fails to download files from the compile farm server. Try recompiling the FPGA VI.
-61323 LabVIEW FPGA: The current target has no available DCMs for the CLIP.
-61322 LabVIEW FPGA: The current target has no available MMCMs for the CLIP.
-61321 LabVIEW FPGA: The compile farm server does not have any compile workers to perform this compilation.
-61320 LabVIEW FPGA: The compile farm server cancelled the compilation.
-61319 LabVIEW FPGA: The compile farm server aborted the compilation.
-61318 LabVIEW FPGA: The compile worker cannot perform the compilation. The compile worker may be configured incorrectly for this compilation or it may be in an error state.
-61317 LabVIEW FPGA: The Xilinx tools required for this compilation are not installed on this machine.
-61316 LabVIEW FPGA: The compile worker is not installed on this machine.
-61315 LabVIEW FPGA: You do not have a license for the compile cloud service or the license has expired.
-61314 LabVIEW FPGA: The disconnected compilation cannot be retrieved from the compile farm server.
-61313 LabVIEW FPGA: The compile farm server returned an invalid username and password combination.
-61312 LabVIEW FPGA: The compile farm server is not installed on this machine.
-61311 LabVIEW FPGA: LabVIEW cannot contact the compile farm server.
-61310 LabVIEW FPGA: A clock is not supported on this target.
-61309 LabVIEW FPGA: A node requires a synchronous reset but the build spec allows enable removal.
-61308 LabVIEW FPGA: A node is not supported when the application allows enable removal.
-61307 LabVIEW FPGA: A node requiring a running clock during reset is in an application allowing enable removal.
-61306 LabVIEW FPGA: This CLIP is not supported for applications that allow enable removal.
-61305 LabVIEW FPGA: This CLIP is not supported for applications that allow enable removal.
-61304 LabVIEW FPGA: The LabVIEW client version is incompatible with the compile server version.
-61303 LabVIEW FPGA: File operation received an empty path.
-61302 LabVIEW FPGA: Changing the logging enable requires a restart.
-61301 LabVIEW FPGA: A reference was accessed that was not allocated.

An internal software error has occurred. Please contact National Instruments technical support at ni.com/support.

-61300 LabVIEW FPGA: User cancelled operation in progress.
-61299 LabVIEW FPGA: A loop requires enable removal but the build spec does not support it.
-61298 LabVIEW FPGA: This target does not support enable removal.
-61297 LabVIEW FPGA: A loop controlled by a clock that does not support gating requires enable removal.
-61296 LabVIEW FPGA: A loop that requires enable removal conditionally stops executing.
-61295 LabVIEW FPGA: A loop that requires enable removal has dataflow dependencies.
-61294 LabVIEW FPGA: The size of the selected data type is too large for the selected DRAM.
-61293 LabVIEW FPGA: Insufficient DRAM available for allocation of memories.
-61292 LabVIEW FPGA: Missing Method(s) for DRAM-based memory.
-61291 LabVIEW FPGA: Request Data and Retrieve Data memory methods must be in the same clock domain.
-61290 LabVIEW FPGA: DRAM Memory Method Not Supported Outside SCTL.
-61289 LabVIEW FPGA: In the DRAM Memory Write method, the array size of "Byte Enables" does not match the number of bytes of "Memory In".
-61254 LabVIEW FPGA: This bitfile can run only once. Download the bitfile again before re-running the VI. Ensure the Open FPGA Reference node is not configured to run before Download is called.
-61253 LabVIEW FPGA: LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles that do not support Reset. Instead, right-click the Close FPGA VI Reference function and select Close.
-61252 LabVIEW FPGA: The operation could not be performed because the FPGA is in configuration or discovery mode. Wait for configuration or discovery to complete and retry your operation.
-61251 LabVIEW FPGA: The bitfile is incompatible with the configuration of the FPGA interface reference wire.
-61250 LabVIEW FPGA: Corrupt or missing Xilinx installation.
-61247 LabVIEW FPGA: The VI cannot be compiled for FPGA.
-61246 LabVIEW FPGA: Missing resource definition for FIFO, Memory, or Register method.
-61245 LabVIEW FPGA: The VI cannot be compiled for FPGA.
-61244 LabVIEW FPGA: The VI cannot compile without a block diagram. The LabVIEW FPGA Module does not support VIs saved without block diagrams.
-61243 LabVIEW FPGA: The array does not meet implementation requirements.
-61242 LabVIEW FPGA: The FPGA Module does not support this combination of data types.
-61241 LabVIEW FPGA: Duplicate file error.
-61240 LabVIEW FPGA: Duplicate file error.
-61239 LabVIEW FPGA: FIFO execution is only supported under FPGA targets.
-61238 LabVIEW FPGA: Memory execution is only supported under FPGA targets.
-61237 LabVIEW FPGA: Terminal(s) requiring constant input wired to non-constant source(s).
-61236 LabVIEW FPGA: Terminal(s) requiring constant input unwired.
-61235 LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node corresponds to a FIFO item that does not match the configuration of the FIFO Method Node.
-61234 LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node does not correspond to any FIFO item in the project nor to any VI-defined FIFO.
-61233 LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node is an empty string. Make sure the wired value corresponds to a FIFO item in the project or to a VI-defined FIFO .
-61232 LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node corresponds to a memory item that does not match the configuration of the Memory Method Node.
-61231 LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node does not correspond to a memory item in the project or to any VI-defined memory.
-61230 LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node is an empty string. Make sure the wired value corresponds to a memory item in the project or a VI-defined memory.
-61229 LabVIEW FPGA: The value wired into the Register In input of a Register Method Node corresponds to a Register item that does not match the configuration of the Register Method Node.
-61228 LabVIEW FPGA: The value wired into the Register In input of a Register Method Node does not correspond to a Register item in the project or to any VI-defined Register.
-61227 LabVIEW FPGA: The value wired into the Register In input of a Register Method Node is an empty string. Make sure the wired value corresponds to a Register item in the project or to a VI-defined Register.
-61226 LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node corresponds to a Handshake item that does not match the configuration of the Handshake Method Node.
-61225 LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node does not correspond to a Handshake item in the project or to a VI-defined Handshake.
-61224 LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node is an empty string. Make sure the wired value corresponds to a Handshake item in the project or to a VI-defined Handshake.
-61223 LabVIEW FPGA: Register execution is only supported under FPGA targets.
-61222 LabVIEW FPGA: Handshake execution is only supported under FPGA targets.
-61221 LabVIEW FPGA: Close and reset is not supported when the FPGA target execution mode is configured to Third-Party Simulation.
-61220 LabVIEW FPGA: Invalid memory access.
-61219 LabVIEW FPGA: The number of elements requested must be less than or equal to the number of unacquired elements left in the host memory DMA FIFO. There are currently fewer unacquired elements left in the FIFO than are being requested. Use the Delete Data Value Reference function to release some acquired elements before acquiring more elements.
-61218 LabVIEW FPGA: FIFO.Configure is not supported when configured with greater than 65536 elements and when the FPGA target execution mode is configured to Third-Party Simulation.
-61217 LabVIEW FPGA: A session cannot be closed or reset and a bitfile cannot be downloaded while DMA FIFO region references are outstanding for the specified session. Use a Delete Data Value Reference function to delete any regions acquired from Acquire Read Region or Acquire Write Region before taking any of these actions.
-61216 LabVIEW FPGA: A gated clock has violated the handshaking protocol. If you are using external gated clocks, ensure that they follow the required clock gating protocol. If you are generating your clocks internally, please contact National Instruments Technical Support.
-61215 LabVIEW FPGA: Bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops can run only once. Download the bitfile again before re-running the VI.
-61214 LabVIEW FPGA: For bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops, LabVIEW FPGA does not support this method prior to running the bitfile.
-61213 LabVIEW FPGA: LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops. Instead, right-click the Close FPGA VI Reference function and select Close.
-61212 LabVIEW FPGA: LabVIEW FPGA does not support the Abort method for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops.
-61211 LabVIEW FPGA: LabVIEW FPGA does not support the Reset method for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops.
-61210 LabVIEW FPGA: An error occurred when initializing the LabVIEW FPGA simulation.
-61209 LabVIEW FPGA: This function is not supported when the FPGA target execution mode is configured to Execute VI on Third-Party Simulator.
-61208 LabVIEW FPGA: This function is supported only when the FPGA VI reference is configured for Dynamic mode and the FPGA target execution mode is configured to Execute VI on Third-Party Simulator.
-61207 LabVIEW FPGA: Internal error: DiagramReset did not clear within the timeout period.

Please contact National Instruments Technical Support at ni.com/support.

-61206 LabVIEW FPGA: The configured item does not exist.
-61205 LabVIEW FPGA: An item of the selected name is present but is a different data type than that configured in the Open FPGA VI Reference.
-61204 LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in Simulation mode. Stop all activities on the FPGA before requesting this operation.
-61203 LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in Interactive mode. Stop all activities on the FPGA before requesting this operation.
-61202 LabVIEW FPGA: LabVIEW could not perform the operation because an FPGA VI reference to another VI is currently open. You must close the currently open FPGA VI reference before attempting to perform this operation.
-61201 LabVIEW FPGA: The chassis is in Scan Interface programming mode. In order to run FPGA VIs, you must go to the chassis properties page, select FPGA programming mode, and deploy the settings.
-61200 LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in FPGA Interface C API mode. Stop all activities on the FPGA before requesting this operation.
-61199 LabVIEW FPGA: Execution has terminated because an I/O item that does not support execution on the development computer with real I/O has been encountered.

You can execute an FPGA VI on the development computer with real I/O only when all of the I/O items you use in the FPGA VI support this mode of execution.

-61198 LabVIEW FPGA: Handshake methods are not supported outside SCTLs.
-61197 LabVIEW FPGA: Each handshake cannot support more than one of each type of method.
-61196 LabVIEW FPGA: The handshake Read Without Acknowledge and Acknowledge methods must be used in the same clock domain.
-61195 LabVIEW FPGA: The handshake Read Without Acknowledge and Acknowledge methods cannot be used separately.
-61194 LabVIEW FPGA: You cannot use a handshake Read method with a Read Without Acknowledge or an Acknowledge method.
-61193 LabVIEW FPGA: The handshake is missing a Read or Write method.
-61192 LabVIEW FPGA: A False constant is wired to a DSP48 node enable terminal.
-61191 LabVIEW FPGA: The IP Integration node specifies an incompatible .ngc synthesis file.
-61190 LabVIEW FPGA: Inconsistent clock settings between CLIP declaration file and CLIP instantiation.
-61189 LabVIEW FPGA: CLIP refers to an FPGA clock that does not meet requirements.
-61188 LabVIEW FPGA: CLIP refers to a missing FPGA clock.
-61187 LabVIEW FPGA: Missing CLIP implementation file.
-61186 LabVIEW FPGA: Updated CLIP declaration file.
-61185 LabVIEW FPGA: Missing CLIP declaration.
-61184 LabVIEW FPGA: Incorrectly configured CLIP instance.
-61183 LabVIEW FPGA: The transfer function order exceeds the maximum order allowed.
-61182 LabVIEW FPGA: The transfer function is improper. The order of the numerator must be less than or equal to the order of the denominator.
-61181 LabVIEW FPGA: The notch width or Q factor must be greater than zero.
-61180 LabVIEW FPGA: All frequencies, f, within the notch region must meet: 0 < f < fs/2, where fs is the sample rate.
-61179 LabVIEW FPGA: Unsupported node on this target.
-61178 LabVIEW FPGA: Internal software error(s): Unable to resolve clock for ports.
-61177 LabVIEW FPGA: Missing Read or Write method for FIFO.
-61176 LabVIEW FPGA: Invalid clock utilized for FIFO Method.
-61175 LabVIEW FPGA: FPGA FIFO Node is not wired with constant FPGA FIFO Name.
-61174 LabVIEW FPGA: FPGA Memory Node is not wired with constant FPGA Memory Name.
-61173 LabVIEW FPGA: Item does not match configuration of the name control.
-61172 LabVIEW FPGA: Project item not found.
-61171 LabVIEW FPGA: Name control or constant is empty.
-61170 LabVIEW FPGA: The real and imaginary input data arrays must be the same size.
-61169 LabVIEW FPGA: The input parameter is not achievable on the FPGA at the given clock rate.
-61168 LabVIEW FPGA: The channel index input is out of the range of the configured number of channels.
-61167 LabVIEW FPGA: This function is not supported when the FPGA target is configured for Simulation.
-61166 LabVIEW FPGA: HDL Interface Node file conflict.
-61165 LabVIEW FPGA: You cannot execute this FPGA VI for Simulation because the FPGA VI is broken.
-61164 LabVIEW FPGA: Local and global variables of this type are not supported.
-61163 LabVIEW FPGA: Internal software error(s).
-61162 LabVIEW FPGA: Object must be used inside a single-cycle Timed Loop.
-61161 LabVIEW FPGA: VI Execution Mode not supported outside single-cycle Timed Loop.
-61160 LabVIEW FPGA: VI Execution Mode not supported inside single-cycle Timed Loop.
-61159 LabVIEW FPGA: This function is not supported when the FPGA target is configured for Simulation with Real I/O.
-61158 LabVIEW FPGA: Conditional terminal on For Loop not supported.
-61157 LabVIEW FPGA: Object(s) not supported in the single-cycle Timed Loop.
-61156 LabVIEW FPGA: Clock domain crossing is not supported for Occurrences.
-61155 LabVIEW FPGA: Unsupported Clock For Resource.
-61154 LabVIEW FPGA: Access from different clock domains not supported.
-61153 LabVIEW FPGA: Express VI not configured.
-61152 LabVIEW FPGA: Variable clock rate not supported.
-61151 LabVIEW FPGA: Function or structure must be wired to a fixed clock name.
-61150 LabVIEW FPGA: Clock project item not found.
-61149 LabVIEW FPGA: Clock control or constant is empty.
-61148 LabVIEW FPGA: Clock rate mismatch.
-61147 LabVIEW FPGA: Internal software error(s).
-61146 LabVIEW FPGA: IP Integration Node must have a clock enable port.
-61145 LabVIEW FPGA: HDL Interface Node File Not Found.
-61144 LabVIEW FPGA: HDL Interface Node outside single-cycle Timed Loop.
-61143 LabVIEW FPGA: Front panel control/indicator violates size restrictions.
-61142 LabVIEW FPGA: VI is broken.
-61141 LabVIEW FPGA: The operation could not be performed because the FPGA is busy. Stop all activities on the FPGA before requesting this operation. If the target is in Scan Interface programming mode, put it in FPGA Interface programming mode. If RIO Device Setup or MAX is currently open for downloading a bitfile to flash memory on the device, wait until the download ends.
-61140 LabVIEW FPGA: The VI cannot be compiled because its type is not supported. Only standard VIs can be compiled.
-61139 LabVIEW FPGA: Top-level clock rate has changed.
-61138 LabVIEW FPGA: Invalid top-level clock for target.
-61137 LabVIEW FPGA: Internal software error(s).
-61136 LabVIEW FPGA: Internal software error(s).
-61135 LabVIEW FPGA: Internal software error(s).
-61134 LabVIEW FPGA: HDL Interface Node inside single-cycle Timed Loop.
-61133 LabVIEW FPGA: Front panel control/indicator(s) crossing clock domains not supported in subVIs.
-61132 LabVIEW FPGA: Front panel control/indicator(s) crossing clock domains is not supported in subVIs.
-61131 LabVIEW FPGA: Internal software error(s).
-61130 LabVIEW FPGA: Too many resource interface requestors.
-61129 LabVIEW FPGA: Top-level port has more than one driver.
-61128 LabVIEW FPGA: Internal software error(s).
-61127 LabVIEW FPGA: Internal software error(s).
-61126 LabVIEW FPGA: Internal software error(s).
-61125 LabVIEW FPGA: The top-level port was requested before the selected component created it.
-61124 LabVIEW FPGA: A resource was requested before the resource database was initialized.
-61123 LabVIEW FPGA: Internal software error(s).
-61122 LabVIEW FPGA: Internal software error(s).
-61121 LabVIEW FPGA: Internal software error(s).
-61120 LabVIEW FPGA: Error attempting to remove register from component.
-61119 LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
-61118 LabVIEW FPGA: Unsupported function inputs.
-61117 LabVIEW FPGA: Unsupported function inputs.
-61116 LabVIEW FPGA: Unsupported Compound Arithmetic inputs.
-61115 LabVIEW FPGA: Non-reentrant subVI(s) used in different clock domains.
-61114 LabVIEW FPGA: Non-reentrant subVI(s) used inside and outside a single-cycle Timed Loop.
-61113 LabVIEW FPGA: Constant references not allowed.
-61112 LabVIEW FPGA: The method(s) are used in multiple clock domains.
-61111 LabVIEW FPGA: Object(s) only supported in the single-cycle Timed Loop.
-61110 LabVIEW FPGA: Invalid FIFO implementation.
-61109 LabVIEW FPGA: Object(s) connected to an initialized shift register.
-61108 LabVIEW FPGA: Resource interface(s) requested from both inside and outside the single-cycle Timed Loop.
-61107 LabVIEW FPGA: Arbitration option not supported inside a single-cycle Timed Loop.
-61106 LabVIEW FPGA: Multiple instances of non-reentrant subVI(s) in the single-cycle Timed Loop.
-61105 LabVIEW FPGA: Multiple writes to control/indicator and local(s) in single-cycle Timed Loops.
-61104 LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
-61103 LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
-61102 LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
-61101 LabVIEW FPGA: Object(s) not supported in the single-cycle Timed Loop.
-61100 LabVIEW FPGA: The Interrupt function cannot wait until its interrupt is cleared in a single-cycle Timed Loop.
-61099 LabVIEW FPGA: Built-in FIFO used in external clock domain.
-61098 LabVIEW FPGA: Derived clock required.
-61097 LabVIEW FPGA: CLIP simulation model not defined.
-61096 LabVIEW FPGA: Memory is read-only with a type defined by a custom control.
-61095 LabVIEW FPGA: Object without implicit enable signal is used outside a single-cycle Timed Loop.
-61094 LabVIEW FPGA: Object not supported in simulation.
-61093 LabVIEW FPGA: Object without implicit enable in Case structure.
-61092 LabVIEW FPGA: Resource does not support single-cycle Timed Loops.
-61091 LabVIEW FPGA: Resource requires use inside single-cycle Timed Loop.
-61090 LabVIEW FPGA: Resource used in unsupported clock domain.
-61089 LabVIEW FPGA: Uninitialized read-only memory.
-61088 LabVIEW FPGA: Built-in FIFO not supported on current target.
-61087 LabVIEW FPGA: Files changed requiring node reconfiguration.
-61086 LabVIEW FPGA: File(s) do not exist.
-61085 LabVIEW FPGA: IP not supported on current target.
-61084 LabVIEW FPGA: Relative clock rate mismatch.
-61083 LabVIEW FPGA: A hardware clocking error occurred. A derived clock lost lock with its base clock during the execution of the FPGA VI. If any base clocks with derived clocks are referencing an external source, make sure that the external source is connected and within the supported frequency, jitter, accuracy, duty cycle, and voltage specifications. Also verify that the characteristics of the base clock match the configuration specified in the FPGA Base Clock Properties dialog box. If all base clocks with derived clocks are generated from free-running, on-board sources, please contact National Instruments technical support at ni.com/support.
-61082 LabVIEW FPGA: The current target does not have sufficient DMA control line sets available.
-61081 LabVIEW FPGA: Insufficient DMA channels available on the current target.
-61080 LabVIEW FPGA: This target does not support FPGA interrupts.
-61079 LabVIEW FPGA: Insufficient address space on the FPGA for certain registers.
-61078 LabVIEW FPGA: The requested memory could not be allocated.
-61077 LabVIEW FPGA: Terminated DMA FIFO. The FPGA was reconfigured while the DMA FIFO was in use.
-61076 LabVIEW FPGA: The DMA transfer did not complete within the timeout period.
-61075 LabVIEW FPGA: The DMA transfer was aborted and did not complete.
-61074 LabVIEW FPGA: The timeout parameter must be -1, 0, or a positive integer.
-61073 LabVIEW FPGA: The number of elements to read or write must be less than or equal to the depth of the host memory DMA FIFO.
-61072 LabVIEW FPGA: The requested FIFO depth is invalid. It is either 0 or an amount not supported by the hardware.
-61071 LabVIEW FPGA: The selected DMA FIFO was not found in the bitfile or FPGA design or is out of sync with the bitfile.
-61070 LabVIEW FPGA: The compiled bitfile for the specified VI contains information that is no longer valid or is corrupt.

Recompile the VI to correct this error.

-61069 LabVIEW FPGA: This bitfile was created in a more recent version of LabVIEW and is incompatible with this version.
-61068 LabVIEW FPGA: Unrelated over clock error.
-61067 LabVIEW FPGA: Clock resource limit exceeded.
-61066 LabVIEW FPGA: Incompatible clock domains between FIFO count method and FIFO write/read method.
-61065 LabVIEW FPGA: Digital resource access conflict.
-61064 LabVIEW FPGA: HDL Interface Node configured to require clock during reset.
-61063 LabVIEW FPGA: Component requires a running clock during reset.
-61062 LabVIEW FPGA: Internal software error(s).
-61061 LabVIEW FPGA: Nested libraries are currently not supported in FPGA VIs.
-61060 LabVIEW FPGA: Clock domain crossing is not selected for the memory item.
-61059 LabVIEW FPGA: The selected control was not found or is out of sync.
-61058 LabVIEW FPGA: Loops using external clocks must never exit.
-61057 LabVIEW FPGA: Internal software error(s).
-61056 LabVIEW FPGA: Top-level clock cannot be enabled/disabled at run time.
-61055 LabVIEW FPGA: Clock requires enable and disable but is not programmed.
-61054 LabVIEW FPGA: Cannot enable or disable a clock in the same clock domain being enabled or disabled.
-61053 LabVIEW FPGA: Insufficient DMA channels available.
-61052 LabVIEW FPGA: FIFO missing a function.
-61051 LabVIEW FPGA: Multiple FIFOs using the same DMA channel.
-61050 LabVIEW FPGA: Clock domain crossing is not supported for FIFO implementation.
-61049 LabVIEW FPGA: Enabling and disabling a clock requires the clock support run-time enable and disable.
-61048 LabVIEW FPGA: This target does not support DMA output from the host to the target.
-61047 LabVIEW FPGA: Controls or indicators using Synchronous Display are not supported in single-cycle Timed Loops.
-61046 LabVIEW FPGA: An error was detected in the communication between the host computer and the FPGA target.

If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.

-61045 LabVIEW FPGA: Usage of locals is restricted on synchronous controls/indicators.
-61044 LabVIEW FPGA: The target does not have enough address space to accommodate the number of registers requested.
-61043 LabVIEW FPGA: Internal software error(s).
-61042 LabVIEW FPGA: Internal software error(s).
-61041 LabVIEW FPGA: Register name conflict.
-61040 LabVIEW FPGA: Unsupported access strategy.
-61039 LabVIEW FPGA: Clock resource limit exceeded.
-61038 LabVIEW FPGA: Millisecond timing resolution not supported.
-61037 LabVIEW FPGA: Clock requested for From-To constraint does not exist.
-61036 LabVIEW FPGA: Microsecond timing resolution not supported.
-61035 LabVIEW FPGA: Microsecond/Millisecond timing resolution not supported.
-61034 LabVIEW FPGA: Invalid top-level clock for target.
-61033 LabVIEW FPGA: Two timing sources in this application have the same clock signal name.
-61032 LabVIEW FPGA: The available hardware cannot generate a derived clock.
-61031 LabVIEW FPGA: There are no configured clocks for this application. Please configure a clock in the project tree.
-61030 LabVIEW FPGA: Clock resource limit exceeded.
-61029 LabVIEW FPGA: VHDL signal names for clocks must contain "Clk" or "Clock". The first letter can be upper or lower case, but subsequent letters must be lower case.
-61028 LabVIEW FPGA: A plug-in developer for a LV FPGA target did not provide timing constraints for all top level clocks.
-61027 LabVIEW FPGA: Clock resource limit exceeded.
-61026 LabVIEW FPGA: A clock name was found that is not configured.
-61025 LabVIEW FPGA: Enabling/Disabling derived clocks not supported.
-61024 LabVIEW FPGA: The device type that has been configured in this function does not match the actual type of the device.
-61023 LabVIEW FPGA: The device at the address that was configured in this function is no longer available.
-61022 LabVIEW FPGA: The FPGA target does not support running the FPGA VI in simulation mode.
-61021 LabVIEW FPGA: FPGA Interface is out of date with the FPGA VI. Right-click and select Refresh.
-61020 LabVIEW FPGA: FIFO timeout not supported.
-61019 LabVIEW FPGA: A digital I/O resource cannot be accessed in a single-cycle Timed Loop from both a Digital Output function and a Digital Port Output function.
-61018 LabVIEW FPGA: An error occurred downloading the VI to the FPGA device.

Verify that the target is connected and powered and that the resource of the target is properly configured.

-61017 LabVIEW FPGA: You must recompile the VI for the selected target.
-61016 LabVIEW FPGA: You must compile the VI for this target.
-61015 LabVIEW FPGA: No bitfile was found for download. You must compile the VI for this target.
-61014 LabVIEW FPGA: The device does not exist or is not accepting any connections.

Possible Reasons: -The resource for the target is not correct or the target resource specified does not exist. -If the target is located remotely:

   A. The remote system might be turned off.
   B. The software to use the device on the remote system might not be properly installed.
   C. You might not have networking properly configured to access the remote system.
   D. You might not have permissions properly set for any servers used to access the target.
-61013 LabVIEW FPGA: The FIFO Method Node reached the timeout before being able to access the FIFO. This error is due to another FIFO Method Node accessing the same FIFO and not completing before the current method timed out.
-61012 LabVIEW FPGA: The FPGA VI reference used to initialize the FIFO is no longer valid.
-61011 LabVIEW FPGA: Unsupported FIFO size.
-61010 LabVIEW FPGA: You are trying to read from, write to, or close a FIFO that has not been initialized by the InitFIFO method.
-61009 LabVIEW FPGA: Unresolved LabVIEW class.
-61008 LabVIEW FPGA: Class control or indicator on top-level VI.
-61007 LabVIEW FPGA: Conditional Disable Structure contains broken code.
-61006 LabVIEW FPGA: Syntax error in user supplied HDL.
-61005 LabVIEW FPGA: Object not supported in simulation.
-61004 LabVIEW FPGA: FIFO object not supported in simulation.
-61003 LabVIEW FPGA: You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop.
-61002 LabVIEW FPGA: The array size exceeds the limit for the current node when the node is inside a single-cycle Timed Loop.
61003 LabVIEW FPGA: The FPGA VI specified by the Invoke Method function with the Run method is already running.
61004 LabVIEW FPGA: Occurrence traceback failed.
61005 LabVIEW FPGA: Bad Clock Rate for operation.
61006 LabVIEW FPGA: The alias used by this FPGA Device I/O function, I/O Method Node, or I/O Property Node does not exist.
61050 LabVIEW FPGA: A parameter to a function is invalid.
61051 LabVIEW FPGA: An operation did not complete because requested memory was unavailable.
61052 LabVIEW FPGA: HDL code generation error occurred.
61053 LabVIEW FPGA: A resource management error occurred. The resources might have conflicting configurations.
61054 LabVIEW FPGA: A code generation error occurred while interpreting LabVIEW signals.
61055 LabVIEW FPGA: Internal software error(s).
61056 LabVIEW FPGA: Timing specified in the diagram cannot be met.
61057 LabVIEW FPGA: Internally pipelined object(s) not connected to enough Feedback Nodes.
61058 LabVIEW FPGA: Invalid clock for single-cycle Timed Loop.
61059 LabVIEW FPGA: Invalid initialization option on a Feedback Node that follows a Memory Read method.
61060 LabVIEW FPGA: The Wait on IRQ method timed out before the specified interrupt was received.
61061 LabVIEW FPGA: Unsupported delay on Feedback Node following memory read.
61062 LabVIEW FPGA: Invalid use of the enable terminal on a Feedback Node that follows a Memory Read method.
61063 LabVIEW FPGA: Initializer constant is wired through a tunnel.
61064 LabVIEW FPGA: Internal software error(s).
61211 LabVIEW FPGA: Multiple resources with the same name are present in this VI. The Dynamic Mode of the FPGA Interface can only access a single resource of a given name.
61347 LabVIEW FPGA: This compile has exceeded the amount of data that can be streamed from the server