GLA Summit 2025/High-Speed Visualization of Any of Your FPGA Wires
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| Conference | GLA Summit 2025 |
| Presenters | Anders Sekanina |
High-Speed Visualization of Any of Your FPGA Wires by Anders Sekanina
Have you ever used FIFO to stream high-speed data from your FPGA target to the host? But after compiling your FPGA, you realize you'd rather stream another signal—then you need to recompile. Could there be a way to do this dynamically so that you can select which signals to stream at runtime? In this presentation, I will show how I have developed a FIFO-based system to high-speed monitor (or write) a large number of signals in FPGA code. It is used in projects ranging from motor control in medical rehabilitation equipment to hardware-in-the-loop engine simulation.