NI HSAI-RIO Config Error Code Family: Difference between revisions
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! Description | ! Description | ||
|- | |- | ||
| | | -1074101504 | ||
| Configuration error. | | Configuration error. | ||
|- | |- | ||
| | | -1074101503 | ||
| The class called does not implement this method. Use a child class that implements this method. | | The class called does not implement this method. Use a child class that implements this method. | ||
|- | |- | ||
| | | -1074101502 | ||
| Onboard PLL failed to lock. | | Onboard PLL failed to lock. | ||
|- | |- | ||
| | | -1074101501 | ||
| FPGA PLL failed to lock. | | FPGA PLL failed to lock. | ||
|- | |- | ||
| | | -1074101500 | ||
| ADC PLL failed to lock. | | ADC PLL failed to lock. | ||
|- | |- | ||
| | | -1074101499 | ||
| ADC config error. | | ADC config error. | ||
|- | |- | ||
| | | -1074101498 | ||
| Invalid value. | | Invalid value. | ||
|- | |- | ||
| | | -1074101497 | ||
| One or more channels are overloaded. | | One or more channels are overloaded. | ||
|- | |- | ||
| | | -1074101496 | ||
| One or more DRAM Banks failed to initialize. | | One or more DRAM Banks failed to initialize. | ||
|- | |- | ||
| | | -1074101495 | ||
| The revision of the Configuration library compiled into the FPGA bitfile is too new for the current Host software. Upgrade the software to a version compatible with the revision of the Configuration library contained in the FPGA bitfile. Alternatively, recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. | | The revision of the Configuration library compiled into the FPGA bitfile is too new for the current Host software. Upgrade the software to a version compatible with the revision of the Configuration library contained in the FPGA bitfile. Alternatively, recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. | ||
|- | |- | ||
| | | -1074101494 | ||
| The revision of the Configuration library compiled into the FPGA bitfile is too old for the current Host software. Recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. Alternatively, downgrade the software to a version compatible with the revision of the Configuration library compiled into the FPGA bitfile. | | The revision of the Configuration library compiled into the FPGA bitfile is too old for the current Host software. Recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. Alternatively, downgrade the software to a version compatible with the revision of the Configuration library compiled into the FPGA bitfile. | ||
|- | |- | ||
| | | -1074101493 | ||
| A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. | | A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. | ||
|- | |- | ||
| | | -1074101492 | ||
| A hardware failure related to the power rails on the daughtercard has occurred. | | A hardware failure related to the power rails on the daughtercard has occurred. | ||
|- | |- | ||
| | | -1074101491 | ||
| ADC communication error has occurred. Re-download the FPGA or reboot the system. If the error persists, contact NI technical support at ni.com/support. | | ADC communication error has occurred. Re-download the FPGA or reboot the system. If the error persists, contact NI technical support at ni.com/support. | ||
|- | |- | ||
| | | -1074101490 | ||
| A device initialization error has occurred. Re-download the FPGA or power cycle your chassis. | | A device initialization error has occurred. Re-download the FPGA or power cycle your chassis. | ||
|- | |- | ||
| | | -1074101414 | ||
| The current clocking configuration does not support export clock. Reconfigure the clock to a supported clocking configuration listed in the help manual. | | The current clocking configuration does not support export clock. Reconfigure the clock to a supported clocking configuration listed in the help manual. | ||
|- | |- | ||
| | | -1074101413 | ||
| The current clocking configuration does not support phase DAC adjustment. Reconfigure the clock to a supported clocking configuration listed in the help manual. | | The current clocking configuration does not support phase DAC adjustment. Reconfigure the clock to a supported clocking configuration listed in the help manual. | ||
|- | |- | ||
| | | 1073382155 | ||
| A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. | | A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. | ||
|- | |- | ||
| | | 1073382156 | ||
| A hardware failure related to the power rails on the daughtercard has occurred. | | A hardware failure related to the power rails on the daughtercard has occurred. | ||
|} | |} | ||
[[Category:Error Handling]] | [[Category:Error Handling]] | ||
Latest revision as of 15:55, 7 May 2023
Below are all of the Error Codes that belong to the NI HSAI-RIO Config Error Code Family (see Error List for list of Families).
| Code | Description |
|---|---|
| -1074101504 | Configuration error. |
| -1074101503 | The class called does not implement this method. Use a child class that implements this method. |
| -1074101502 | Onboard PLL failed to lock. |
| -1074101501 | FPGA PLL failed to lock. |
| -1074101500 | ADC PLL failed to lock. |
| -1074101499 | ADC config error. |
| -1074101498 | Invalid value. |
| -1074101497 | One or more channels are overloaded. |
| -1074101496 | One or more DRAM Banks failed to initialize. |
| -1074101495 | The revision of the Configuration library compiled into the FPGA bitfile is too new for the current Host software. Upgrade the software to a version compatible with the revision of the Configuration library contained in the FPGA bitfile. Alternatively, recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. |
| -1074101494 | The revision of the Configuration library compiled into the FPGA bitfile is too old for the current Host software. Recompile the FPGA bitfile or obtain a new FPGA bitfile that uses a version of the Configuration FPGA library compatible with the software. Alternatively, downgrade the software to a version compatible with the revision of the Configuration library compiled into the FPGA bitfile. |
| -1074101493 | A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. |
| -1074101492 | A hardware failure related to the power rails on the daughtercard has occurred. |
| -1074101491 | ADC communication error has occurred. Re-download the FPGA or reboot the system. If the error persists, contact NI technical support at ni.com/support. |
| -1074101490 | A device initialization error has occurred. Re-download the FPGA or power cycle your chassis. |
| -1074101414 | The current clocking configuration does not support export clock. Reconfigure the clock to a supported clocking configuration listed in the help manual. |
| -1074101413 | The current clocking configuration does not support phase DAC adjustment. Reconfigure the clock to a supported clocking configuration listed in the help manual. |
| 1073382155 | A clock fault has occurred. Re-download the FPGA or reboot the system. To avoid this error in future, connect an external clock with correct frequency and power at all times while the ADC clock is configured for an external source. Before removing the external clock, disable the FPGA data clock or reconfigure the ADC clock to an internal source. |
| 1073382156 | A hardware failure related to the power rails on the daughtercard has occurred. |