View source for LabVIEW FPGA Error Code Family

Below are all of the Error Codes that belong to the '''LabVIEW FPGA''' Error Code Family (see [[Error List]] for list of Families).

{| class="wikitable sortable"
! Code
! Description
|-
| [[Error Code -61515|-61515]]
| LabVIEW FPGA: Local variables are not allowed in the top-level VI in IP export.
|-
| [[Error Code -61514|-61514]]
| LabVIEW FPGA: This function or VI is not allowed in IP export.
|-
| [[Error Code -61513|-61513]]
| LabVIEW FPGA: This node is not allowed in IP export.
|-
| [[Error Code -61512|-61512]]
| LabVIEW FPGA: The destination directory path cannot contain parentheses.
|-
| [[Error Code -61511|-61511]]
| LabVIEW FPGA: Unsupported file type.
|-
| [[Error Code -61510|-61510]]
| LabVIEW FPGA: Cannot access distributed RAM from different clock domains.
|-
| [[Error Code -61509|-61509]]
| LabVIEW FPGA: Unsupported number of elements per read or write on the current target.
|-
| [[Error Code -61508|-61508]]
| LabVIEW FPGA: Node not supported in single-cycle Timed Loops.
|-
| [[Error Code -61507|-61507]]
| LabVIEW FPGA: Peer-to-peer FIFOs are unsupported on the current target.
|-
| [[Error Code -61506|-61506]]
| LabVIEW FPGA: The FPGA VI configured for running in simulation mode contains controls or indicators with duplicate names. The Read/Write function cannot read from or write to controls or indicators with duplicate names. Rename the controls or indicators.
|-
| [[Error Code -61505|-61505]]
| LabVIEW FPGA: Unsupported .xci file.
|-
| [[Error Code -61504|-61504]]
| LabVIEW FPGA: Unsupported FIFO method.
|-
| [[Error Code -61503|-61503]]
| LabVIEW FPGA: Missing required Xilinx compilation tools.
|-
| [[Error Code -61502|-61502]]
| LabVIEW FPGA: File format mismatch.
|-
| [[Error Code -61501|-61501]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61500|-61500]]
| LabVIEW FPGA: An internal software error has occurred.  Please contact National Instruments technical support at ni.com/support with the following information:

LabVIEW could not read a CLIP XML file.
|-
| [[Error Code -61499|-61499]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support.
|-
| [[Error Code -61498|-61498]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

Required tag was not found in the resource file.
|-
| [[Error Code -61497|-61497]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

An unsupported register offset was requested.
|-
| [[Error Code -61496|-61496]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

An unexpected case was reached.
|-
| [[Error Code -61495|-61495]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

A path tag specified a value that is not a path.
|-
| [[Error Code -61494|-61494]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

An IP Generator VI did not match the required interface.
|-
| [[Error Code -61493|-61493]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

The specified IP Generator VI could not be found.
|-
| [[Error Code -61492|-61492]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

Error accessing FPGA provider.
|-
| [[Error Code -61491|-61491]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

An IP Generator is missing the required VI Path Tag.
|-
| [[Error Code -61490|-61490]]
| LabVIEW FPGA: An internal error has occurred.
|-
| [[Error Code -61489|-61489]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61488|-61488]]
| LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support with following information:

A required XML tag was not found.
|-
| [[Error Code -61487|-61487]]
| LabVIEW FPGA: This channel control or indicator is on the top-level VI.
|-
| [[Error Code -61475|-61475]]
| LabVIEW FPGA: The XML tag "DramAddressBitAlignment" is missing from the target resource XML file. For more details consult LabVIEW_FPGA_PlugInManual.doc.
|-
| [[Error Code -61474|-61474]]
| LabVIEW FPGA: "FFT size" must be greater than or equal to the number of samples per input.
|-
| [[Error Code -61473|-61473]]
| LabVIEW FPGA: The "imaginary data" input array size is different from that of the "real data" input. The array sizes of these inputs must be the same.
|-
| [[Error Code -61472|-61472]]
| LabVIEW FPGA: The input array size must be 2, 4, 8, or 16.
|-
| [[Error Code -61471|-61471]]
| LabVIEW FPGA: You must reload the IO Module declaration file.
|-
| [[Error Code -61470|-61470]]
| LabVIEW FPGA: You must reload the DRAM declaration file.
|-
| [[Error Code -61469|-61469]]
| LabVIEW FPGA: Invalid size for Stream or Lossy Stream channel writer.
|-
| [[Error Code -61468|-61468]]
| LabVIEW FPGA: A channel terminal of a non-reentrant subVI is connected to multiple channels.
|-
| [[Error Code -61467|-61467]]
| LabVIEW FPGA: Stream or Lossy Stream writer endpoints not wired correctly.
|-
| [[Error Code -61466|-61466]]
| LabVIEW FPGA: LabVIEW encountered an error when trying to run the Vivado Design Suite scripts.
|-
| [[Error Code -61465|-61465]]
| LabVIEW FPGA: LabVIEW failed to delete a file.
|-
| [[Error Code -61464|-61464]]
| LabVIEW FPGA: LabVIEW failed to delete a file.
|-
| [[Error Code -61463|-61463]]
| LabVIEW FPGA: LabVIEW failed to export project for the Vivado Design Suite.
|-
| [[Error Code -61462|-61462]]
| LabVIEW FPGA: The design was unable to meet timing requirements due to a pulse width violation.
|-
| [[Error Code -61461|-61461]]
| LabVIEW FPGA: This version of LabVIEW does not support the requested FPGA compilation tools.
|-
| [[Error Code -61460|-61460]]
| LabVIEW FPGA: Control and indicator names with newline characters are only supported when the VI execution mode is set to Simulation (Simulated I/O) and the FPGA VI reference is configured for Dynamic mode.
|-
| [[Error Code -61459|-61459]]
| LabVIEW FPGA: The selected target requires 64-bit Xilinx tools, but the system uses a 32-bit OS.
|-
| [[Error Code -61458|-61458]]
| LabVIEW FPGA: Target does not support terminals configured for variable and bounded size arrays.
|-
| [[Error Code -61457|-61457]]
| LabVIEW FPGA: The compilation status file is missing or corrupt.
|-
| [[Error Code -61456|-61456]]
| LabVIEW FPGA: The FPGA design did not meet timing requirements and the source of the timing failure could not be located automatically.
|-
| [[Error Code -61455|-61455]]
| LabVIEW FPGA: Some of the compilation steps were not executed.
|-
| [[Error Code -61454|-61454]]
| LabVIEW FPGA: Some signals were not properly constrained in the design.
|-
| [[Error Code -61453|-61453]]
| LabVIEW FPGA: The constraints file was not used in the compilation.
|-
| [[Error Code -61452|-61452]]
| LabVIEW FPGA: The compilation failed due to resource overmapping.
|-
| [[Error Code -61451|-61451]]
| LabVIEW FPGA: The compilation failed due to timing violations.
|-
| [[Error Code -61450|-61450]]
| LabVIEW FPGA: The compilation failed due to a Xilinx error.
|-
| [[Error Code -61449|-61449]]
| LabVIEW FPGA: The FPGA VI has finished executing.
|-
| [[Error Code -61448|-61448]]
| LabVIEW FPGA: The simulation is not running.
|-
| [[Error Code -61447|-61447]]
| LabVIEW FPGA: LabVIEW cannot locate the VI.
|-
| [[Error Code -61446|-61446]]
| LabVIEW FPGA: The execution mode is invalid for the Desktop Execution Node.
|-
| [[Error Code -61445|-61445]]
| LabVIEW FPGA: The handshake is outside a single-cycle Timed Loop.
|-
| [[Error Code -61444|-61444]]
| LabVIEW FPGA: The Desktop Execution Node is misconfigured.
|-
| [[Error Code -61443|-61443]]
| LabVIEW FPGA: The simulation has exceeded the maximum simulated time.
|-
| [[Error Code -61442|-61442]]
| LabVIEW FPGA: The FPGA Desktop Execution Node cannot run the configured VI.
|-
| [[Error Code -61441|-61441]]
| LabVIEW FPGA: Another FPGA VI for this target is already executing on the development computer. Stop the other VI before running this VI.
|-
| [[Error Code -61417|-61417]]
| LabVIEW FPGA: The method does not support FIFOs with the "UltraRAM" implementation.
|-
| [[Error Code -61416|-61416]]
| LabVIEW FPGA: The current target does not support FIFOs with the UltraRAM implementation.
|-
| [[Error Code -61415|-61415]]
| LabVIEW FPGA: The method does not support FIFOs with the "Built-In" control logic.
|-
| [[Error Code -61414|-61414]]
| LabVIEW FPGA: Control or indicator data type is not supported.
|-
| [[Error Code -61413|-61413]]
| LabVIEW FPGA: FIFO with handshaking interface is outside a single-cycle Timed Loop.
|-
| [[Error Code -61412|-61412]]
| LabVIEW FPGA: Missing feedback node after Ready For Input terminal.
|-
| [[Error Code -61411|-61411]]
| LabVIEW FPGA: FIFO invokes methods with incompatible interfaces.
|-
| [[Error Code -61410|-61410]]
| LabVIEW FPGA: Target does not support the handshaking interface on this FIFO.
|-
| [[Error Code -61408|-61408]]
| LabVIEW FPGA: Feedback Node initialization unsupported.
|-
| [[Error Code -61406|-61406]]
| LabVIEW FPGA: The logic in a socketed CLIP is preventing the FPGA VI from running.
|-
| [[Error Code -61405|-61405]]
| LabVIEW FPGA: The operation failed because you do not have a physical target specified for this FPGA target. 

Right-click the FPGA target in the Project Explorer window, select Properties, and enter an FPGA target resource name in the Resource text box.
|-
| [[Error Code -61404|-61404]]
| LabVIEW FPGA: LabVIEW encountered a target-specific error or warning.
|-
| [[Error Code -61403|-61403]]
| LabVIEW FPGA: LabVIEW is unable to interact with the current target because a required file is missing or inaccessible. Check that the FPGA target-specific driver software is installed correctly.
|-
| [[Error Code -61402|-61402]]
| LabVIEW FPGA: LabVIEW lost communication with the device. 

The resource for the target was disconnected or removed.

If the target is located remotely, the remote system might be turned off or there might be a network problem.
|-
| [[Error Code -61400|-61400]]
| LabVIEW FPGA: Operation failed because the type of the hardware specified in the project and/or in the VI does not match the type of the hardware that was physically accessed.
|-
| [[Error Code -61399|-61399]]
| LabVIEW FPGA: Execution of the FPGA VI on the development computer is not supported for the given item/node in the custom VI used for FPGA I/O.
|-
| [[Error Code -61398|-61398]]
| LabVIEW FPGA: FPGA VI simulation failed because either the path for the specified custom VI for FPGA I/O simulation is missing or incorrect, or the specified custom VI for FPGA I/O simulation uses an incorrect connector pane. Check the custom VI path on the Simulation page of the target settings or check that the VI matches the required interface.
|-
| [[Error Code -61397|-61397]]
| LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O does not conform to the calling requirements of the FPGA VI.
|-
| [[Error Code -61396|-61396]]
| LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O called a VI or a function that returned an error.
|-
| [[Error Code -61395|-61395]]
| LabVIEW FPGA: Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O is not executable.
|-
| [[Error Code -61394|-61394]]
| LabVIEW FPGA: This VI is supported only when the Execution Stage is Running.
|-
| [[Error Code -61355|-61355]]
| LabVIEW FPGA: An internal software error has occurred. DFIR refnum not found.
|-
| [[Error Code -61354|-61354]]
| LabVIEW FPGA: Internal software error(s): Connected node is not constant.
|-
| [[Error Code -61353|-61353]]
| LabVIEW FPGA: Internal software error(s): Output terminal not supported.
|-
| [[Error Code -61352|-61352]]
| LabVIEW FPGA: Internal software error(s): Terminal is not connectable.
|-
| [[Error Code -61351|-61351]]
| LabVIEW FPGA: Internal software error(s): Terminal is unconnected.
|-
| [[Error Code -61350|-61350]]
| LabVIEW FPGA: Internal software error(s): Terminal Index Out of Bounds.
|-
| [[Error Code -61347|-61347]]
| LabVIEW FPGA: The user has reached the maximum number of simultaneous compiles for this compile cloud account.
|-
| [[Error Code -61346|-61346]]
| LabVIEW FPGA: The FPGA Compile Farm Server does not support the current version of the FPGA Module. Use a compatible version of the FPGA Compile Farm Server or switch to another server. Refer to the FPGA Module readme for information about FPGA Module versions supported by this version of FPGA Compile Farm Server.
|-
| [[Error Code -61345|-61345]]
| LabVIEW FPGA: Unresolved LabVIEW class.
|-
| [[Error Code -61344|-61344]]
| LabVIEW FPGA: The array contains arrays of varying sizes.
|-
| [[Error Code -61343|-61343]]
| LabVIEW FPGA: Unresolved LabVIEW class.
|-
| [[Error Code -61342|-61342]]
| LabVIEW FPGA: The compile farm server returned an unexpected software error.
|-
| [[Error Code -61341|-61341]]
| LabVIEW FPGA: The array contains arrays of varying sizes.
|-
| [[Error Code -61340|-61340]]
| LabVIEW FPGA: The compilation failed because the system ran out of memory.
|-
| [[Error Code -61339|-61339]]
| LabVIEW FPGA: The top-level VI contains a variable-sized array control or indicator.
|-
| [[Error Code -61338|-61338]]
| LabVIEW FPGA: Array does not resolve to a fixed size.
|-
| [[Error Code -61337|-61337]]
| LabVIEW FPGA: Array does not resolve to a fixed size.
|-
| [[Error Code -61336|-61336]]
| LabVIEW FPGA: The While Loop contains an auto-indexed output tunnel.
|-
| [[Error Code -61335|-61335]]
| LabVIEW FPGA: Array does not resolve to a fixed size.
|-
| [[Error Code -61334|-61334]]
| LabVIEW FPGA: Array does not resolve to a fixed size.
|-
| [[Error Code -61333|-61333]]
| LabVIEW FPGA: Array does not resolve to a fixed size.
|-
| [[Error Code -61332|-61332]]
| LabVIEW FPGA: An unexpected error occurred with the compilation tools. Trying to compile the FPGA VI again might resolve the issue.
|-
| [[Error Code -61331|-61331]]
| LabVIEW FPGA: The UnitOfWork file sent to the Compile Worker was malformed.
|-
| [[Error Code -61330|-61330]]
| LabVIEW FPGA: An internal software error in the compile worker has occurred.
|-
| [[Error Code -61329|-61329]]
| LabVIEW FPGA: The LabVIEW FPGA Module fails to download files from the compile farm server. Try recompiling the FPGA VI.
|-
| [[Error Code -61323|-61323]]
| LabVIEW FPGA: The current target has no available DCMs for the CLIP.
|-
| [[Error Code -61322|-61322]]
| LabVIEW FPGA: The current target has no available MMCMs for the CLIP.
|-
| [[Error Code -61321|-61321]]
| LabVIEW FPGA: The compile farm server does not have any compile workers to perform this compilation.
|-
| [[Error Code -61320|-61320]]
| LabVIEW FPGA: The compile farm server cancelled the compilation.
|-
| [[Error Code -61319|-61319]]
| LabVIEW FPGA: The compile farm server aborted the compilation.
|-
| [[Error Code -61318|-61318]]
| LabVIEW FPGA: The compile worker cannot perform the compilation. The compile worker may be configured incorrectly for this compilation or it may be in an error state.
|-
| [[Error Code -61317|-61317]]
| LabVIEW FPGA: The Xilinx tools required for this compilation are not installed on this machine.
|-
| [[Error Code -61316|-61316]]
| LabVIEW FPGA: The compile worker is not installed on this machine.
|-
| [[Error Code -61315|-61315]]
| LabVIEW FPGA: You do not have a license for the compile cloud service or the license has expired.
|-
| [[Error Code -61314|-61314]]
| LabVIEW FPGA: The disconnected compilation cannot be retrieved from the compile farm server.
|-
| [[Error Code -61313|-61313]]
| LabVIEW FPGA: The compile farm server returned an invalid username and password combination.
|-
| [[Error Code -61312|-61312]]
| LabVIEW FPGA: The compile farm server is not installed on this machine.
|-
| [[Error Code -61311|-61311]]
| LabVIEW FPGA: LabVIEW cannot contact the compile farm server.
|-
| [[Error Code -61310|-61310]]
| LabVIEW FPGA: A clock is not supported on this target.
|-
| [[Error Code -61309|-61309]]
| LabVIEW FPGA: A node requires a synchronous reset but the build spec allows enable removal.
|-
| [[Error Code -61308|-61308]]
| LabVIEW FPGA: A node is not supported when the application allows enable removal.
|-
| [[Error Code -61307|-61307]]
| LabVIEW FPGA: A node requiring a running clock during reset is in an application allowing enable removal.
|-
| [[Error Code -61306|-61306]]
| LabVIEW FPGA: This CLIP is not supported for applications that allow enable removal.
|-
| [[Error Code -61305|-61305]]
| LabVIEW FPGA: This CLIP is not supported for applications that allow enable removal.
|-
| [[Error Code -61304|-61304]]
| LabVIEW FPGA: The LabVIEW client version is incompatible with the compile server version.
|-
| [[Error Code -61303|-61303]]
| LabVIEW FPGA: File operation received an empty path.
|-
| [[Error Code -61302|-61302]]
| LabVIEW FPGA: Changing the logging enable requires a restart.
|-
| [[Error Code -61301|-61301]]
| LabVIEW FPGA: A reference was accessed that was not allocated.
An internal software error has occurred.  Please contact National Instruments technical support at ni.com/support.
|-
| [[Error Code -61300|-61300]]
| LabVIEW FPGA: User cancelled operation in progress.
|-
| [[Error Code -61299|-61299]]
| LabVIEW FPGA: A loop requires enable removal but the build spec does not support it.
|-
| [[Error Code -61298|-61298]]
| LabVIEW FPGA: This target does not support enable removal.
|-
| [[Error Code -61297|-61297]]
| LabVIEW FPGA: A loop controlled by a clock that does not support gating requires enable removal.
|-
| [[Error Code -61296|-61296]]
| LabVIEW FPGA: A loop that requires enable removal conditionally stops executing.
|-
| [[Error Code -61295|-61295]]
| LabVIEW FPGA: A loop that requires enable removal has dataflow dependencies.
|-
| [[Error Code -61294|-61294]]
| LabVIEW FPGA: The size of the selected data type is too large for the selected DRAM.
|-
| [[Error Code -61293|-61293]]
| LabVIEW FPGA: Insufficient DRAM available for allocation of memories.
|-
| [[Error Code -61292|-61292]]
| LabVIEW FPGA: Missing Method(s) for DRAM-based memory.
|-
| [[Error Code -61291|-61291]]
| LabVIEW FPGA: Request Data and Retrieve Data memory methods must be in the same clock domain.
|-
| [[Error Code -61290|-61290]]
| LabVIEW FPGA: DRAM Memory Method Not Supported Outside SCTL.
|-
| [[Error Code -61289|-61289]]
| LabVIEW FPGA: In the DRAM Memory Write method, the array size of "Byte Enables" does not match the number of bytes of "Memory In".
|-
| [[Error Code -61254|-61254]]
| LabVIEW FPGA: This bitfile can run only once. Download the bitfile again before re-running the VI. Ensure the Open FPGA Reference node is not configured to run before Download is called.
|-
| [[Error Code -61253|-61253]]
| LabVIEW FPGA: LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles that do not support Reset. Instead, right-click the Close FPGA VI Reference function and select Close.
|-
| [[Error Code -61252|-61252]]
| LabVIEW FPGA: The operation could not be performed because the FPGA is in configuration or discovery mode. Wait for configuration or discovery to complete and retry your operation.
|-
| [[Error Code -61251|-61251]]
| LabVIEW FPGA: The bitfile is incompatible with the configuration of the FPGA interface reference wire.
|-
| [[Error Code -61250|-61250]]
| LabVIEW FPGA: Corrupt or missing Xilinx installation.
|-
| [[Error Code -61247|-61247]]
| LabVIEW FPGA: The VI cannot be compiled for FPGA.
|-
| [[Error Code -61246|-61246]]
| LabVIEW FPGA: Missing resource definition for FIFO, Memory, or Register method.
|-
| [[Error Code -61245|-61245]]
| LabVIEW FPGA: The VI cannot be compiled for FPGA.
|-
| [[Error Code -61244|-61244]]
| LabVIEW FPGA: The VI cannot compile without a block diagram. The LabVIEW FPGA Module does not support VIs saved without block diagrams.
|-
| [[Error Code -61243|-61243]]
| LabVIEW FPGA: The array does not meet implementation requirements.
|-
| [[Error Code -61242|-61242]]
| LabVIEW FPGA: The FPGA Module does not support this combination of data types.
|-
| [[Error Code -61241|-61241]]
| LabVIEW FPGA: Duplicate file error.
|-
| [[Error Code -61240|-61240]]
| LabVIEW FPGA: Duplicate file error.
|-
| [[Error Code -61239|-61239]]
| LabVIEW FPGA: FIFO execution is only supported under FPGA targets.
|-
| [[Error Code -61238|-61238]]
| LabVIEW FPGA: Memory execution is only supported under FPGA targets.
|-
| [[Error Code -61237|-61237]]
| LabVIEW FPGA: Terminal(s) requiring constant input wired to non-constant source(s).
|-
| [[Error Code -61236|-61236]]
| LabVIEW FPGA: Terminal(s) requiring constant input unwired.
|-
| [[Error Code -61235|-61235]]
| LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node corresponds to a FIFO item that does not match the configuration of the FIFO Method Node.
|-
| [[Error Code -61234|-61234]]
| LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node does not correspond to any FIFO item in the project nor to any VI-defined FIFO.
|-
| [[Error Code -61233|-61233]]
| LabVIEW FPGA: The value wired into the FIFO In input of a FIFO Method Node is an empty string.  Make sure the wired value corresponds to a FIFO item in the project or to a VI-defined FIFO .
|-
| [[Error Code -61232|-61232]]
| LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node corresponds to a memory item that does not match the configuration of the Memory Method Node.
|-
| [[Error Code -61231|-61231]]
| LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node does not correspond to a memory item in the project or to any VI-defined memory.
|-
| [[Error Code -61230|-61230]]
| LabVIEW FPGA: The value wired into the Memory In input of a Memory Method Node is an empty string.  Make sure the wired value corresponds to a memory item in the project or a VI-defined memory.
|-
| [[Error Code -61229|-61229]]
| LabVIEW FPGA: The value wired into the Register In input of a Register Method Node corresponds to a Register item that does not match the configuration of the Register Method Node.
|-
| [[Error Code -61228|-61228]]
| LabVIEW FPGA: The value wired into the Register In input of a Register Method Node does not correspond to a Register item in the project or to any VI-defined Register.
|-
| [[Error Code -61227|-61227]]
| LabVIEW FPGA: The value wired into the Register In input of a Register Method Node is an empty string.  Make sure the wired value corresponds to a Register item in the project or to a VI-defined Register.
|-
| [[Error Code -61226|-61226]]
| LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node corresponds to a Handshake item that does not match the configuration of the Handshake Method Node.
|-
| [[Error Code -61225|-61225]]
| LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node does not correspond to a Handshake item in the project or to a VI-defined Handshake.
|-
| [[Error Code -61224|-61224]]
| LabVIEW FPGA: The value wired into the Handshake In input of a Handshake Method Node is an empty string.  Make sure the wired value corresponds to a Handshake item in the project or to a VI-defined Handshake.
|-
| [[Error Code -61223|-61223]]
| LabVIEW FPGA: Register execution is only supported under FPGA targets.
|-
| [[Error Code -61222|-61222]]
| LabVIEW FPGA: Handshake execution is only supported under FPGA targets.
|-
| [[Error Code -61221|-61221]]
| LabVIEW FPGA: Close and reset is not supported when the FPGA target execution mode is configured to Third-Party Simulation.
|-
| [[Error Code -61220|-61220]]
| LabVIEW FPGA: Invalid memory access.
|-
| [[Error Code -61219|-61219]]
| LabVIEW FPGA: The number of elements requested must be less than or equal to the number of unacquired elements left in the host memory DMA FIFO. There are currently fewer unacquired elements left in the FIFO than are being requested. Use the Delete Data Value Reference function to release some acquired elements before acquiring more elements.
|-
| [[Error Code -61218|-61218]]
| LabVIEW FPGA: FIFO.Configure is not supported when configured with greater than 65536 elements and when the FPGA target execution mode is configured to Third-Party Simulation.
|-
| [[Error Code -61217|-61217]]
| LabVIEW FPGA: A session cannot be closed or reset and a bitfile cannot be downloaded while DMA FIFO region references are outstanding for the specified session. Use a Delete Data Value Reference function to delete any regions acquired from Acquire Read Region or Acquire Write Region before taking any of these actions.
|-
| [[Error Code -61216|-61216]]
| LabVIEW FPGA: A gated clock has violated the handshaking protocol. If you are using external gated clocks, ensure that they follow the required clock gating protocol. If you are generating your clocks internally, please contact National Instruments Technical Support.
|-
| [[Error Code -61215|-61215]]
| LabVIEW FPGA: Bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops can run only once. Download the bitfile again before re-running the VI.
|-
| [[Error Code -61214|-61214]]
| LabVIEW FPGA: For bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops, LabVIEW FPGA does not support this method prior to running the bitfile.
|-
| [[Error Code -61213|-61213]]
| LabVIEW FPGA: LabVIEW FPGA does not support Close and Reset if Last Reference for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops. Instead, right-click the Close FPGA VI Reference function and select Close.
|-
| [[Error Code -61212|-61212]]
| LabVIEW FPGA: LabVIEW FPGA does not support the Abort method for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops.
|-
| [[Error Code -61211|-61211]]
| LabVIEW FPGA: LabVIEW FPGA does not support the Reset method for bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops.
|-
| [[Error Code -61210|-61210]]
| LabVIEW FPGA: An error occurred when initializing the LabVIEW FPGA simulation.
|-
| [[Error Code -61209|-61209]]
| LabVIEW FPGA: This function is not supported when the FPGA target execution mode is configured to Execute VI on Third-Party Simulator.
|-
| [[Error Code -61208|-61208]]
| LabVIEW FPGA: This function is supported only when the FPGA VI reference is configured for Dynamic mode and the FPGA target execution mode is configured to Execute VI on Third-Party Simulator.
|-
| [[Error Code -61207|-61207]]
| LabVIEW FPGA: Internal error: DiagramReset did not clear within the timeout period.

Please contact National Instruments Technical Support at ni.com/support.
|-
| [[Error Code -61206|-61206]]
| LabVIEW FPGA: The configured item does not exist.
|-
| [[Error Code -61205|-61205]]
| LabVIEW FPGA: An item of the selected name is present but is a different data type than that configured in the Open FPGA VI Reference.
|-
| [[Error Code -61204|-61204]]
| LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in Simulation mode. Stop all activities on the FPGA before requesting this operation.
|-
| [[Error Code -61203|-61203]]
| LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in Interactive mode. Stop all activities on the FPGA before requesting this operation.
|-
| [[Error Code -61202|-61202]]
| LabVIEW FPGA: LabVIEW could not perform the operation because an FPGA VI reference to another VI is currently open. You must close the currently open FPGA VI reference before attempting to perform this operation.
|-
| [[Error Code -61201|-61201]]
| LabVIEW FPGA: The chassis is in Scan Interface programming mode. In order to run FPGA VIs, you must go to the chassis properties page, select FPGA programming mode, and deploy the settings.
|-
| [[Error Code -61200|-61200]]
| LabVIEW FPGA: The operation could not be performed because the FPGA is busy operating in FPGA Interface C API mode. Stop all activities on the FPGA before requesting this operation.
|-
| [[Error Code -61199|-61199]]
| LabVIEW FPGA: Execution has terminated because an I/O item that does not support execution on the development computer with real I/O has been encountered.

You can execute an FPGA VI on the development computer with real I/O only when all of the I/O items you use in the FPGA VI support this mode of execution.
|-
| [[Error Code -61198|-61198]]
| LabVIEW FPGA: Handshake methods are not supported outside SCTLs.
|-
| [[Error Code -61197|-61197]]
| LabVIEW FPGA: Each handshake cannot support more than one of each type of method.
|-
| [[Error Code -61196|-61196]]
| LabVIEW FPGA: The handshake Read Without Acknowledge and Acknowledge methods must be used in the same clock domain.
|-
| [[Error Code -61195|-61195]]
| LabVIEW FPGA: The handshake Read Without Acknowledge and Acknowledge methods cannot be used separately.
|-
| [[Error Code -61194|-61194]]
| LabVIEW FPGA: You cannot use a handshake Read method with a Read Without Acknowledge or an Acknowledge method.
|-
| [[Error Code -61193|-61193]]
| LabVIEW FPGA: The handshake is missing a Read or Write method.
|-
| [[Error Code -61192|-61192]]
| LabVIEW FPGA: A False constant is wired to a DSP48 node enable terminal.
|-
| [[Error Code -61191|-61191]]
| LabVIEW FPGA: The IP Integration node specifies an incompatible .ngc synthesis file.
|-
| [[Error Code -61190|-61190]]
| LabVIEW FPGA: Inconsistent clock settings between CLIP declaration file and CLIP instantiation.
|-
| [[Error Code -61189|-61189]]
| LabVIEW FPGA: CLIP refers to an FPGA clock that does not meet requirements.
|-
| [[Error Code -61188|-61188]]
| LabVIEW FPGA: CLIP refers to a missing FPGA clock.
|-
| [[Error Code -61187|-61187]]
| LabVIEW FPGA: Missing CLIP implementation file.
|-
| [[Error Code -61186|-61186]]
| LabVIEW FPGA: Updated CLIP declaration file.
|-
| [[Error Code -61185|-61185]]
| LabVIEW FPGA: Missing CLIP declaration.
|-
| [[Error Code -61184|-61184]]
| LabVIEW FPGA: Incorrectly configured CLIP instance.
|-
| [[Error Code -61183|-61183]]
| LabVIEW FPGA: The transfer function order exceeds the maximum order allowed.
|-
| [[Error Code -61182|-61182]]
| LabVIEW FPGA: The transfer function is improper. The order of the numerator must be less than or equal to the order of the denominator.
|-
| [[Error Code -61181|-61181]]
| LabVIEW FPGA: The notch width or Q factor must be greater than zero.
|-
| [[Error Code -61180|-61180]]
| LabVIEW FPGA: All frequencies, f, within the notch region must meet: 0 < f < fs/2, where fs is the sample rate.
|-
| [[Error Code -61179|-61179]]
| LabVIEW FPGA: Unsupported node on this target.
|-
| [[Error Code -61178|-61178]]
| LabVIEW FPGA: Internal software error(s): Unable to resolve clock for ports.
|-
| [[Error Code -61177|-61177]]
| LabVIEW FPGA: Missing Read or Write method for FIFO.
|-
| [[Error Code -61176|-61176]]
| LabVIEW FPGA: Invalid clock utilized for FIFO Method.
|-
| [[Error Code -61175|-61175]]
| LabVIEW FPGA: FPGA FIFO Node is not wired with constant FPGA FIFO Name.
|-
| [[Error Code -61174|-61174]]
| LabVIEW FPGA: FPGA Memory Node is not wired with constant FPGA Memory Name.
|-
| [[Error Code -61173|-61173]]
| LabVIEW FPGA: Item does not match configuration of the name control.
|-
| [[Error Code -61172|-61172]]
| LabVIEW FPGA: Project item not found.
|-
| [[Error Code -61171|-61171]]
| LabVIEW FPGA: Name control or constant is empty.
|-
| [[Error Code -61170|-61170]]
| LabVIEW FPGA: The real and imaginary input data arrays must be the same size.
|-
| [[Error Code -61169|-61169]]
| LabVIEW FPGA: The input parameter is not achievable on the FPGA at the given clock rate.
|-
| [[Error Code -61168|-61168]]
| LabVIEW FPGA: The channel index input is out of the range of the configured number of channels.
|-
| [[Error Code -61167|-61167]]
| LabVIEW FPGA: This function is not supported when the FPGA target is configured for Simulation.
|-
| [[Error Code -61166|-61166]]
| LabVIEW FPGA: HDL Interface Node file conflict.
|-
| [[Error Code -61165|-61165]]
| LabVIEW FPGA: You cannot execute this FPGA VI for Simulation because the FPGA VI is broken.
|-
| [[Error Code -61164|-61164]]
| LabVIEW FPGA: Local and global variables of this type are not supported.
|-
| [[Error Code -61163|-61163]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61162|-61162]]
| LabVIEW FPGA: Object must be used inside a single-cycle Timed Loop.
|-
| [[Error Code -61161|-61161]]
| LabVIEW FPGA: VI Execution Mode not supported outside single-cycle Timed Loop.
|-
| [[Error Code -61160|-61160]]
| LabVIEW FPGA: VI Execution Mode not supported inside single-cycle Timed Loop.
|-
| [[Error Code -61159|-61159]]
| LabVIEW FPGA: This function is not supported when the FPGA target is configured for Simulation with Real I/O.
|-
| [[Error Code -61158|-61158]]
| LabVIEW FPGA: Conditional terminal on For Loop not supported.
|-
| [[Error Code -61157|-61157]]
| LabVIEW FPGA: Object(s) not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61156|-61156]]
| LabVIEW FPGA: Clock domain crossing is not supported for Occurrences.
|-
| [[Error Code -61155|-61155]]
| LabVIEW FPGA: Unsupported Clock For Resource.
|-
| [[Error Code -61154|-61154]]
| LabVIEW FPGA: Access from different clock domains not supported.
|-
| [[Error Code -61153|-61153]]
| LabVIEW FPGA: Express VI not configured.
|-
| [[Error Code -61152|-61152]]
| LabVIEW FPGA: Variable clock rate not supported.
|-
| [[Error Code -61151|-61151]]
| LabVIEW FPGA: Function or structure must be wired to a fixed clock name.
|-
| [[Error Code -61150|-61150]]
| LabVIEW FPGA: Clock project item not found.
|-
| [[Error Code -61149|-61149]]
| LabVIEW FPGA: Clock control or constant is empty.
|-
| [[Error Code -61148|-61148]]
| LabVIEW FPGA: Clock rate mismatch.
|-
| [[Error Code -61147|-61147]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61146|-61146]]
| LabVIEW FPGA: IP Integration Node must have a clock enable port.
|-
| [[Error Code -61145|-61145]]
| LabVIEW FPGA: HDL Interface Node File Not Found.
|-
| [[Error Code -61144|-61144]]
| LabVIEW FPGA: HDL Interface Node outside single-cycle Timed Loop.
|-
| [[Error Code -61143|-61143]]
| LabVIEW FPGA: Front panel control/indicator violates size restrictions.
|-
| [[Error Code -61142|-61142]]
| LabVIEW FPGA: VI is broken.
|-
| [[Error Code -61141|-61141]]
| LabVIEW FPGA: The operation could not be performed because the FPGA is busy. Stop all activities on the FPGA before requesting this operation. If the target is in Scan Interface programming mode, put it in FPGA Interface programming mode. If RIO Device Setup or MAX is currently open for downloading a bitfile to flash memory on the device, wait until the download ends.
|-
| [[Error Code -61140|-61140]]
| LabVIEW FPGA: The VI cannot be compiled because its type is not supported. Only standard VIs can be compiled.
|-
| [[Error Code -61139|-61139]]
| LabVIEW FPGA: Top-level clock rate has changed.
|-
| [[Error Code -61138|-61138]]
| LabVIEW FPGA: Invalid top-level clock for target.
|-
| [[Error Code -61137|-61137]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61136|-61136]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61135|-61135]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61134|-61134]]
| LabVIEW FPGA: HDL Interface Node inside single-cycle Timed Loop.
|-
| [[Error Code -61133|-61133]]
| LabVIEW FPGA: Front panel control/indicator(s) crossing clock domains not supported in subVIs.
|-
| [[Error Code -61132|-61132]]
| LabVIEW FPGA: Front panel control/indicator(s) crossing clock domains is not supported in subVIs.
|-
| [[Error Code -61131|-61131]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61130|-61130]]
| LabVIEW FPGA: Too many resource interface requestors.
|-
| [[Error Code -61129|-61129]]
| LabVIEW FPGA: Top-level port has more than one driver.
|-
| [[Error Code -61128|-61128]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61127|-61127]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61126|-61126]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61125|-61125]]
| LabVIEW FPGA: The top-level port was requested before the selected component created it.
|-
| [[Error Code -61124|-61124]]
| LabVIEW FPGA: A resource was requested before the resource database was initialized.
|-
| [[Error Code -61123|-61123]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61122|-61122]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61121|-61121]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61120|-61120]]
| LabVIEW FPGA: Error attempting to remove register from component.
|-
| [[Error Code -61119|-61119]]
| LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61118|-61118]]
| LabVIEW FPGA: Unsupported function inputs.
|-
| [[Error Code -61117|-61117]]
| LabVIEW FPGA: Unsupported function inputs.
|-
| [[Error Code -61116|-61116]]
| LabVIEW FPGA: Unsupported Compound Arithmetic inputs.
|-
| [[Error Code -61115|-61115]]
| LabVIEW FPGA: Non-reentrant subVI(s) used in different clock domains.
|-
| [[Error Code -61114|-61114]]
| LabVIEW FPGA: Non-reentrant subVI(s) used inside and outside a single-cycle Timed Loop.
|-
| [[Error Code -61113|-61113]]
| LabVIEW FPGA: Constant references not allowed.
|-
| [[Error Code -61112|-61112]]
| LabVIEW FPGA: The method(s) are used in multiple clock domains.
|-
| [[Error Code -61111|-61111]]
| LabVIEW FPGA: Object(s) only supported in the single-cycle Timed Loop.
|-
| [[Error Code -61110|-61110]]
| LabVIEW FPGA: Invalid FIFO implementation.
|-
| [[Error Code -61109|-61109]]
| LabVIEW FPGA: Object(s) connected to an initialized shift register.
|-
| [[Error Code -61108|-61108]]
| LabVIEW FPGA: Resource interface(s) requested from both inside and outside the single-cycle Timed Loop.
|-
| [[Error Code -61107|-61107]]
| LabVIEW FPGA: Arbitration option not supported inside a single-cycle Timed Loop.
|-
| [[Error Code -61106|-61106]]
| LabVIEW FPGA: Multiple instances of non-reentrant subVI(s) in the single-cycle Timed Loop.
|-
| [[Error Code -61105|-61105]]
| LabVIEW FPGA: Multiple writes to control/indicator and local(s) in single-cycle Timed Loops.
|-
| [[Error Code -61104|-61104]]
| LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61103|-61103]]
| LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61102|-61102]]
| LabVIEW FPGA: Arbitration option not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61101|-61101]]
| LabVIEW FPGA: Object(s) not supported in the single-cycle Timed Loop.
|-
| [[Error Code -61100|-61100]]
| LabVIEW FPGA: The Interrupt function cannot wait until its interrupt is cleared in a single-cycle Timed Loop.
|-
| [[Error Code -61099|-61099]]
| LabVIEW FPGA: Built-in FIFO used in external clock domain.
|-
| [[Error Code -61098|-61098]]
| LabVIEW FPGA: Derived clock required.
|-
| [[Error Code -61097|-61097]]
| LabVIEW FPGA: CLIP simulation model not defined.
|-
| [[Error Code -61096|-61096]]
| LabVIEW FPGA: Memory is read-only with a type defined by a custom control.
|-
| [[Error Code -61095|-61095]]
| LabVIEW FPGA: Object without implicit enable signal is used outside a single-cycle Timed Loop.
|-
| [[Error Code -61094|-61094]]
| LabVIEW FPGA: Object not supported in simulation.
|-
| [[Error Code -61093|-61093]]
| LabVIEW FPGA: Object without implicit enable in Case structure.
|-
| [[Error Code -61092|-61092]]
| LabVIEW FPGA: Resource does not support single-cycle Timed Loops.
|-
| [[Error Code -61091|-61091]]
| LabVIEW FPGA: Resource requires use inside single-cycle Timed Loop.
|-
| [[Error Code -61090|-61090]]
| LabVIEW FPGA: Resource used in unsupported clock domain.
|-
| [[Error Code -61089|-61089]]
| LabVIEW FPGA: Uninitialized read-only memory.
|-
| [[Error Code -61088|-61088]]
| LabVIEW FPGA: Built-in FIFO not supported on current target.
|-
| [[Error Code -61087|-61087]]
| LabVIEW FPGA: Files changed requiring node reconfiguration.
|-
| [[Error Code -61086|-61086]]
| LabVIEW FPGA: File(s) do not exist.
|-
| [[Error Code -61085|-61085]]
| LabVIEW FPGA: IP not supported on current target.
|-
| [[Error Code -61084|-61084]]
| LabVIEW FPGA: Relative clock rate mismatch.
|-
| [[Error Code -61083|-61083]]
| LabVIEW FPGA: A hardware clocking error occurred. A derived clock lost lock with its base clock during the execution of the FPGA VI. If any base clocks with derived clocks are referencing an external source, make sure that the external source is connected and within the supported frequency, jitter, accuracy, duty cycle, and voltage specifications. Also verify that the characteristics of the base clock match the configuration specified in the FPGA Base Clock Properties dialog box. If all base clocks with derived clocks are generated from free-running, on-board sources, please contact National Instruments technical support at ni.com/support.
|-
| [[Error Code -61082|-61082]]
| LabVIEW FPGA: The current target does not have sufficient DMA control line sets available.
|-
| [[Error Code -61081|-61081]]
| LabVIEW FPGA: Insufficient DMA channels available on the current target.
|-
| [[Error Code -61080|-61080]]
| LabVIEW FPGA: This target does not support FPGA interrupts.
|-
| [[Error Code -61079|-61079]]
| LabVIEW FPGA: Insufficient address space on the FPGA for certain registers.
|-
| [[Error Code -61078|-61078]]
| LabVIEW FPGA: The requested memory could not be allocated.
|-
| [[Error Code -61077|-61077]]
| LabVIEW FPGA: Terminated DMA FIFO. The FPGA was reconfigured while the DMA FIFO was in use.
|-
| [[Error Code -61076|-61076]]
| LabVIEW FPGA: The DMA transfer did not complete within the timeout period.
|-
| [[Error Code -61075|-61075]]
| LabVIEW FPGA: The DMA transfer was aborted and did not complete.
|-
| [[Error Code -61074|-61074]]
| LabVIEW FPGA: The timeout parameter must be -1, 0, or a positive integer.
|-
| [[Error Code -61073|-61073]]
| LabVIEW FPGA: The number of elements to read or write must be less than or equal to the depth of the host memory DMA FIFO.
|-
| [[Error Code -61072|-61072]]
| LabVIEW FPGA: The requested FIFO depth is invalid. It is either 0 or an amount not supported by the hardware.
|-
| [[Error Code -61071|-61071]]
| LabVIEW FPGA: The selected DMA FIFO was not found in the bitfile or FPGA design or is out of sync with the bitfile.
|-
| [[Error Code -61070|-61070]]
| LabVIEW FPGA: The compiled bitfile for the specified VI contains information that is no longer valid or is corrupt. 

Recompile the VI to correct this error.
|-
| [[Error Code -61069|-61069]]
| LabVIEW FPGA: This bitfile was created in a more recent version of LabVIEW and is incompatible with this version.
|-
| [[Error Code -61068|-61068]]
| LabVIEW FPGA: Unrelated over clock error.
|-
| [[Error Code -61067|-61067]]
| LabVIEW FPGA: Clock resource limit exceeded.
|-
| [[Error Code -61066|-61066]]
| LabVIEW FPGA: Incompatible clock domains between FIFO count method and FIFO write/read method.
|-
| [[Error Code -61065|-61065]]
| LabVIEW FPGA: Digital resource access conflict.
|-
| [[Error Code -61064|-61064]]
| LabVIEW FPGA: HDL Interface Node configured to require clock during reset.
|-
| [[Error Code -61063|-61063]]
| LabVIEW FPGA: Component requires a running clock during reset.
|-
| [[Error Code -61062|-61062]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61061|-61061]]
| LabVIEW FPGA: Nested libraries are currently not supported in FPGA VIs.
|-
| [[Error Code -61060|-61060]]
| LabVIEW FPGA: Clock domain crossing is not selected for the memory item.
|-
| [[Error Code -61059|-61059]]
| LabVIEW FPGA: The selected control was not found or is out of sync.
|-
| [[Error Code -61058|-61058]]
| LabVIEW FPGA: Loops using external clocks must never exit.
|-
| [[Error Code -61057|-61057]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61056|-61056]]
| LabVIEW FPGA: Top-level clock cannot be enabled/disabled at run time.
|-
| [[Error Code -61055|-61055]]
| LabVIEW FPGA: Clock requires enable and disable but is not programmed.
|-
| [[Error Code -61054|-61054]]
| LabVIEW FPGA: Cannot enable or disable a clock in the same clock domain being enabled or disabled.
|-
| [[Error Code -61053|-61053]]
| LabVIEW FPGA: Insufficient DMA channels available.
|-
| [[Error Code -61052|-61052]]
| LabVIEW FPGA: FIFO missing a function.
|-
| [[Error Code -61051|-61051]]
| LabVIEW FPGA: Multiple FIFOs using the same DMA channel.
|-
| [[Error Code -61050|-61050]]
| LabVIEW FPGA: Clock domain crossing is not supported for FIFO implementation.
|-
| [[Error Code -61049|-61049]]
| LabVIEW FPGA: Enabling and disabling a clock requires the clock support run-time enable and disable.
|-
| [[Error Code -61048|-61048]]
| LabVIEW FPGA: This target does not support DMA output from the host to the target.
|-
| [[Error Code -61047|-61047]]
| LabVIEW FPGA: Controls or indicators using Synchronous Display are not supported in single-cycle Timed Loops.
|-
| [[Error Code -61046|-61046]]
| LabVIEW FPGA: An error was detected in the communication between the host computer and the FPGA target.

If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.
|-
| [[Error Code -61045|-61045]]
| LabVIEW FPGA: Usage of locals is restricted on synchronous controls/indicators.
|-
| [[Error Code -61044|-61044]]
| LabVIEW FPGA: The target does not have enough address space to accommodate the number of registers requested.
|-
| [[Error Code -61043|-61043]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61042|-61042]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code -61041|-61041]]
| LabVIEW FPGA: Register name conflict.
|-
| [[Error Code -61040|-61040]]
| LabVIEW FPGA: Unsupported access strategy.
|-
| [[Error Code -61039|-61039]]
| LabVIEW FPGA: Clock resource limit exceeded.
|-
| [[Error Code -61038|-61038]]
| LabVIEW FPGA: Millisecond timing resolution not supported.
|-
| [[Error Code -61037|-61037]]
| LabVIEW FPGA: Clock requested for From-To constraint does not exist.
|-
| [[Error Code -61036|-61036]]
| LabVIEW FPGA: Microsecond timing resolution not supported.
|-
| [[Error Code -61035|-61035]]
| LabVIEW FPGA: Microsecond/Millisecond timing resolution not supported.
|-
| [[Error Code -61034|-61034]]
| LabVIEW FPGA: Invalid top-level clock for target.
|-
| [[Error Code -61033|-61033]]
| LabVIEW FPGA: Two timing sources in this application have the same clock signal name.
|-
| [[Error Code -61032|-61032]]
| LabVIEW FPGA: The available hardware cannot generate a derived clock.
|-
| [[Error Code -61031|-61031]]
| LabVIEW FPGA: There are no configured clocks for this application. Please configure a clock in the project tree.
|-
| [[Error Code -61030|-61030]]
| LabVIEW FPGA: Clock resource limit exceeded.
|-
| [[Error Code -61029|-61029]]
| LabVIEW FPGA: VHDL signal names for clocks must contain "Clk" or "Clock". The first letter can be upper or lower case, but subsequent letters must be lower case.
|-
| [[Error Code -61028|-61028]]
| LabVIEW FPGA: A plug-in developer for a LV FPGA target did not provide timing constraints for all top level clocks.
|-
| [[Error Code -61027|-61027]]
| LabVIEW FPGA: Clock resource limit exceeded.
|-
| [[Error Code -61026|-61026]]
| LabVIEW FPGA: A clock name was found that is not configured.
|-
| [[Error Code -61025|-61025]]
| LabVIEW FPGA: Enabling/Disabling derived clocks not supported.
|-
| [[Error Code -61024|-61024]]
| LabVIEW FPGA: The device type that has been configured in this function does not match the actual type of the device.
|-
| [[Error Code -61023|-61023]]
| LabVIEW FPGA: The device at the address that was configured in this function is no longer available.
|-
| [[Error Code -61022|-61022]]
| LabVIEW FPGA: The FPGA target does not support running the FPGA VI in simulation mode.
|-
| [[Error Code -61021|-61021]]
| LabVIEW FPGA: FPGA Interface is out of date with the FPGA VI. Right-click and select Refresh.
|-
| [[Error Code -61020|-61020]]
| LabVIEW FPGA: FIFO timeout not supported.
|-
| [[Error Code -61019|-61019]]
| LabVIEW FPGA: A digital I/O resource cannot be accessed in a single-cycle Timed Loop from both a Digital Output function and a Digital Port Output function.
|-
| [[Error Code -61018|-61018]]
| LabVIEW FPGA: An error occurred downloading the VI to the FPGA device.

Verify that the target is connected and powered and that the resource of the target is properly configured.
|-
| [[Error Code -61017|-61017]]
| LabVIEW FPGA: You must recompile the VI for the selected target.
|-
| [[Error Code -61016|-61016]]
| LabVIEW FPGA: You must compile the VI for this target.
|-
| [[Error Code -61015|-61015]]
| LabVIEW FPGA: No bitfile was found for download. You must compile the VI for this target.
|-
| [[Error Code -61014|-61014]]
| LabVIEW FPGA: The device does not exist or is not accepting any connections.

Possible Reasons: 
-The resource for the target is not correct or the target resource specified does not exist.
-If the target is located remotely:
    A. The remote system might be turned off.
    B. The software to use the device on the remote system might not be properly installed.
    C. You might not have networking properly configured to access the remote system.
    D. You might not have permissions properly set for any servers used to access the target.
|-
| [[Error Code -61013|-61013]]
| LabVIEW FPGA: The FIFO Method Node reached the timeout before being able to access the FIFO. This error is due to another FIFO Method Node accessing the same FIFO and not completing before the current method timed out.
|-
| [[Error Code -61012|-61012]]
| LabVIEW FPGA: The FPGA VI reference used to initialize the FIFO is no longer valid.
|-
| [[Error Code -61011|-61011]]
| LabVIEW FPGA: Unsupported FIFO size.
|-
| [[Error Code -61010|-61010]]
| LabVIEW FPGA: You are trying to read from, write to, or close a FIFO that has not been initialized by the InitFIFO method.
|-
| [[Error Code -61009|-61009]]
| LabVIEW FPGA: Unresolved LabVIEW class.
|-
| [[Error Code -61008|-61008]]
| LabVIEW FPGA: Class control or indicator on top-level VI.
|-
| [[Error Code -61007|-61007]]
| LabVIEW FPGA: Conditional Disable Structure contains broken code.
|-
| [[Error Code -61006|-61006]]
| LabVIEW FPGA: Syntax error in user supplied HDL.
|-
| [[Error Code -61005|-61005]]
| LabVIEW FPGA: Object not supported in simulation.
|-
| [[Error Code -61004|-61004]]
| LabVIEW FPGA: FIFO object not supported in simulation.
|-
| [[Error Code -61003|-61003]]
| LabVIEW FPGA: You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop.
|-
| [[Error Code -61002|-61002]]
| LabVIEW FPGA: The array size exceeds the limit for the current node when the node is inside a single-cycle Timed Loop.
|-
| [[Error Code 61003|61003]]
| LabVIEW FPGA: The FPGA VI specified by the Invoke Method function with the Run method is already running.
|-
| [[Error Code 61004|61004]]
| LabVIEW FPGA: Occurrence traceback failed.
|-
| [[Error Code 61005|61005]]
| LabVIEW FPGA: Bad Clock Rate for operation.
|-
| [[Error Code 61006|61006]]
| LabVIEW FPGA: The alias used by this FPGA Device I/O function,  I/O Method Node, or I/O Property Node does not exist.
|-
| [[Error Code 61050|61050]]
| LabVIEW FPGA: A parameter to a function is invalid.
|-
| [[Error Code 61051|61051]]
| LabVIEW FPGA: An operation did not complete because requested memory was unavailable.
|-
| [[Error Code 61052|61052]]
| LabVIEW FPGA: HDL code generation error occurred.
|-
| [[Error Code 61053|61053]]
| LabVIEW FPGA: A resource management error occurred. The resources might have conflicting configurations.
|-
| [[Error Code 61054|61054]]
| LabVIEW FPGA: A code generation error occurred while interpreting LabVIEW signals.
|-
| [[Error Code 61055|61055]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code 61056|61056]]
| LabVIEW FPGA: Timing specified in the diagram cannot be met.
|-
| [[Error Code 61057|61057]]
| LabVIEW FPGA: Internally pipelined object(s) not connected to enough Feedback Nodes.
|-
| [[Error Code 61058|61058]]
| LabVIEW FPGA: Invalid clock for single-cycle Timed Loop.
|-
| [[Error Code 61059|61059]]
| LabVIEW FPGA: Invalid initialization option on a Feedback Node that follows a Memory Read method.
|-
| [[Error Code 61060|61060]]
| LabVIEW FPGA: The Wait on IRQ method timed out before the specified interrupt was received.
|-
| [[Error Code 61061|61061]]
| LabVIEW FPGA: Unsupported delay on Feedback Node following memory read.
|-
| [[Error Code 61062|61062]]
| LabVIEW FPGA: Invalid use of the enable terminal on a Feedback Node that follows a Memory Read method.
|-
| [[Error Code 61063|61063]]
| LabVIEW FPGA: Initializer constant is wired through a tunnel.
|-
| [[Error Code 61064|61064]]
| LabVIEW FPGA: Internal software error(s).
|-
| [[Error Code 61211|61211]]
| LabVIEW FPGA: Multiple resources with the same name are present in this VI.  The Dynamic Mode of the FPGA Interface can only access a single resource of a given name.
|-
| [[Error Code 61347|61347]]
| LabVIEW FPGA: This compile has exceeded the amount of data that can be streamed from the server
|}

[[Category:Error Handling]]