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	<title>GDevCon-6/The Anatomy of a cRIO Module - Revision history</title>
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	<updated>2026-05-08T10:14:57Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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		<id>https://labviewwiki.org/w/index.php?title=GDevCon-6/The_Anatomy_of_a_cRIO_Module&amp;diff=35903&amp;oldid=prev</id>
		<title>Cordm at 13:38, 5 February 2026</title>
		<link rel="alternate" type="text/html" href="https://labviewwiki.org/w/index.php?title=GDevCon-6/The_Anatomy_of_a_cRIO_Module&amp;diff=35903&amp;oldid=prev"/>
		<updated>2026-02-05T13:38:53Z</updated>

		<summary type="html">&lt;p&gt;&lt;/p&gt;
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				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Revision as of 13:38, 5 February 2026&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot; id=&quot;mw-diff-left-l9&quot;&gt;Line 9:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Line 9:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;|presenters=Gary Boorman&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;|presenters=Gary Boorman&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;|abstract=How does the typical cRIO module work? What happens when a cRIO module is plugged into a chassis?  What happens when a property or invoke node is placed on your FPGA block diagram?  How does the cRIO controller know about the module’s capabilities? Does the cRIO controller really have a backplane?  And why are cRIO modules hot-swappable?&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;|abstract=How does the typical cRIO module work? What happens when a cRIO module is plugged into a chassis?  What happens when a property or invoke node is placed on your FPGA block diagram?  How does the cRIO controller know about the module’s capabilities? Does the cRIO controller really have a backplane?  And why are cRIO modules hot-swappable?&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
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&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;Using information learned from building my own cRIO modules, and from writing the drivers in LabVIEW and XML, to creating an API, this talk will look at some of the magic that happens when a cRIO module is inserted into a chassis, and how the LabVIEW FPGA code interacts with cRIO modules.&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;Using information learned from building my own cRIO modules, and from writing the drivers in LabVIEW and XML, to creating an API, this talk will look at some of the magic that happens when a cRIO module is inserted into a chassis, and how the LabVIEW FPGA code interacts with cRIO modules.&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
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		<author><name>Cordm</name></author>
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	<entry>
		<id>https://labviewwiki.org/w/index.php?title=GDevCon-6/The_Anatomy_of_a_cRIO_Module&amp;diff=35902&amp;oldid=prev</id>
		<title>Cordm: Created page with &quot;{{infobox |category=presentation |icon=GDevConButton.png |presentation-conference=GDevCon-6{{!}}GDevCon#6 |presentation-presenter=Gary Boorman }}  {{presentation |presenters=Gary Boorman |abstract=How does the typical cRIO module work? What happens when a cRIO module is plugged into a chassis?  What happens when a property or invoke node is placed on your FPGA block diagram?  How does the cRIO controller know about the module’s capabilities? Does the cRIO controller re...&quot;</title>
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		<updated>2026-02-05T13:38:10Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;{{infobox |category=presentation |icon=GDevConButton.png |presentation-conference=GDevCon-6{{!}}GDevCon#6 |presentation-presenter=Gary Boorman }}  {{presentation |presenters=Gary Boorman |abstract=How does the typical cRIO module work? What happens when a cRIO module is plugged into a chassis?  What happens when a property or invoke node is placed on your FPGA block diagram?  How does the cRIO controller know about the module’s capabilities? Does the cRIO controller re...&amp;quot;&lt;/p&gt;
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&lt;br /&gt;
Using information learned from building my own cRIO modules, and from writing the drivers in LabVIEW and XML, to creating an API, this talk will look at some of the magic that happens when a cRIO module is inserted into a chassis, and how the LabVIEW FPGA code interacts with cRIO modules.&lt;br /&gt;
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[[Category:GDevCon-6]]&lt;/div&gt;</summary>
		<author><name>Cordm</name></author>
	</entry>
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